| Message ID | 20210112055950.21209-2-samuel@sholland.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | sunxi: Support IRQ wakeup from deep sleep | expand |
On Mon, 11 Jan 2021 23:59:41 -0600, Samuel Holland wrote: > The R_INTC in the A31 and newer sun8i/sun50i SoCs has additional > functionality compared to the sun7i/sun9i NMI controller. Among other > things, it multiplexes access to up to 128 interrupts corresponding to > (and in parallel to) the first 128 GIC SPIs. This means the NMI is no > longer the lowest-numbered hwirq at this irqchip, since it is SPI 32 or > 96 (depending on SoC). hwirq 0 now corresponds to SPI 0, usually UART0. > > To allow access to all multiplexed IRQs, the R_INTC requires a new > binding where the interrupt number matches the GIC interrupt number. > Otherwise, interrupts with hwirq numbers below the NMI would not be > representable in the device tree. > > For simplicity, copy the three-cell GIC binding; this disambiguates > interrupt 0 in the old binding (the NMI) from interrupt 0 in the new > binding (SPI 0) by the number of cells. > > Because the H6 R_INTC has a different mapping from multiplexed IRQs to > top-level register bits, it is no longer compatible with the A31 R_INTC. > > Signed-off-by: Samuel Holland <samuel@sholland.org> > --- > .../allwinner,sun6i-a31-r-intc.yaml | 66 +++++++++++++++++++ > .../allwinner,sun7i-a20-sc-nmi.yaml | 10 --- > 2 files changed, 66 insertions(+), 10 deletions(-) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml new file mode 100644 index 000000000000..50e607e607c8 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A31 NMI/Wakeup Interrupt Controller Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + "#interrupt-cells": + const: 3 + description: + The first cell is GIC_SPI (0), the second cell is the IRQ number, and + the third cell is the trigger type as defined in interrupt.txt in this + directory. + + compatible: + oneOf: + - const: allwinner,sun6i-a31-r-intc + - items: + - enum: + - allwinner,sun8i-a83t-r-intc + - allwinner,sun50i-a64-r-intc + - const: allwinner,sun6i-a31-r-intc + - const: allwinner,sun50i-h6-r-intc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + description: + The GIC interrupt labeled as "External NMI". + + interrupt-controller: true + +required: + - "#interrupt-cells" + - compatible + - reg + - interrupts + - interrupt-controller + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + r_intc: interrupt-controller@1f00c00 { + compatible = "allwinner,sun50i-a64-r-intc", + "allwinner,sun6i-a31-r-intc"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x01f00c00 0x400>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + }; + +... diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml index 4fd1e2780026..7fc9ad5ef38c 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml @@ -22,26 +22,16 @@ properties: compatible: oneOf: - - const: allwinner,sun6i-a31-r-intc - const: allwinner,sun6i-a31-sc-nmi deprecated: true - const: allwinner,sun7i-a20-sc-nmi - - items: - - const: allwinner,sun8i-a83t-r-intc - - const: allwinner,sun6i-a31-r-intc - items: - const: allwinner,sun8i-v3s-nmi - const: allwinner,sun9i-a80-nmi - const: allwinner,sun9i-a80-nmi - - items: - - const: allwinner,sun50i-a64-r-intc - - const: allwinner,sun6i-a31-r-intc - items: - const: allwinner,sun50i-a100-nmi - const: allwinner,sun9i-a80-nmi - - items: - - const: allwinner,sun50i-h6-r-intc - - const: allwinner,sun6i-a31-r-intc reg: maxItems: 1
The R_INTC in the A31 and newer sun8i/sun50i SoCs has additional functionality compared to the sun7i/sun9i NMI controller. Among other things, it multiplexes access to up to 128 interrupts corresponding to (and in parallel to) the first 128 GIC SPIs. This means the NMI is no longer the lowest-numbered hwirq at this irqchip, since it is SPI 32 or 96 (depending on SoC). hwirq 0 now corresponds to SPI 0, usually UART0. To allow access to all multiplexed IRQs, the R_INTC requires a new binding where the interrupt number matches the GIC interrupt number. Otherwise, interrupts with hwirq numbers below the NMI would not be representable in the device tree. For simplicity, copy the three-cell GIC binding; this disambiguates interrupt 0 in the old binding (the NMI) from interrupt 0 in the new binding (SPI 0) by the number of cells. Because the H6 R_INTC has a different mapping from multiplexed IRQs to top-level register bits, it is no longer compatible with the A31 R_INTC. Signed-off-by: Samuel Holland <samuel@sholland.org> --- .../allwinner,sun6i-a31-r-intc.yaml | 66 +++++++++++++++++++ .../allwinner,sun7i-a20-sc-nmi.yaml | 10 --- 2 files changed, 66 insertions(+), 10 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml