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[2/2] arm64: dts: qcom: qrb5165-rb5: switch into using GPIO for SPI0 CS

Message ID 20210204204904.294555-2-dmitry.baryshkov@linaro.org
State New
Headers show
Series [1/2] arm64: dts: qcom: sm8250: add pinctrl for SPI using GPIO as a CS | expand

Commit Message

Dmitry Baryshkov Feb. 4, 2021, 8:49 p.m. UTC 
GENI SPI controller shows several issues if it manages the CS on its own
(see 37dd4b777942 ("arm64: dts: qcom: sc7180: Provide pinconf for SPI to
use GPIO for CS")) for the details. Configure SPI0 CS pin as a GPIO.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

---
 arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 2 ++
 1 file changed, 2 insertions(+)

-- 
2.30.0
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
index 50f94460c970..6098ccba85de 100644
--- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
+++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
@@ -1129,6 +1129,8 @@  &slpi {
 /* CAN */
 &spi0 {
 	status = "okay";
+	pinctrl-0 = <&qup_spi0_cs_gpio>;
+	cs-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
 
 	can@0 {
 		compatible = "microchip,mcp2518fd";