| Message ID | c4b7ae4dd009f563e6786f4a41f09efa38636fb6.1614244789.git.saiprakash.ranjan@codeaurora.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | qcom/sc7280: Enable various hardware blocks on SC7280 SoC | expand |
Quoting Sai Prakash Ranjan (2021-02-25 01:30:19) > Add a DT node for Last level cache (aka. system cache) > controller which provides control over the last level > cache present on SC7280 SoC. > > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org> Should add system-cache-controller to the devicetree spec. Or just use cache-controller for the node name.
On 2021-02-26 01:07, Stephen Boyd wrote: > Quoting Sai Prakash Ranjan (2021-02-25 01:30:19) >> Add a DT node for Last level cache (aka. system cache) >> controller which provides control over the last level >> cache present on SC7280 SoC. >> >> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> >> --- > > Reviewed-by: Stephen Boyd <swboyd@chromium.org> > > Should add system-cache-controller to the devicetree spec. Or just use > cache-controller for the node name. This was as per discussion in [1][2] where dt-schema throws an error since it expects cache-level to be associated with cache-controller. [1] https://lore.kernel.org/lkml/5dcd8588.1c69fb81.2528a.3460@mx.google.com/ [2] https://lore.kernel.org/lkml/cover.1573814758.git.saiprakash.ranjan@codeaurora.org/ Thanks, Sai
Quoting Sai Prakash Ranjan (2021-02-26 00:04:27) > On 2021-02-26 01:07, Stephen Boyd wrote: > > Quoting Sai Prakash Ranjan (2021-02-25 01:30:19) > >> Add a DT node for Last level cache (aka. system cache) > >> controller which provides control over the last level > >> cache present on SC7280 SoC. > >> > >> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > >> --- > > > > Reviewed-by: Stephen Boyd <swboyd@chromium.org> > > > > Should add system-cache-controller to the devicetree spec. Or just use > > cache-controller for the node name. > > This was as per discussion in [1][2] where dt-schema throws an error > since it expects cache-level to be associated with cache-controller. > Ah right. Can you add system-cache-controller to the dt spec?
On 2021-02-27 00:15, Stephen Boyd wrote: > Quoting Sai Prakash Ranjan (2021-02-26 00:04:27) >> On 2021-02-26 01:07, Stephen Boyd wrote: >> > Quoting Sai Prakash Ranjan (2021-02-25 01:30:19) >> >> Add a DT node for Last level cache (aka. system cache) >> >> controller which provides control over the last level >> >> cache present on SC7280 SoC. >> >> >> >> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> >> >> --- >> > >> > Reviewed-by: Stephen Boyd <swboyd@chromium.org> >> > >> > Should add system-cache-controller to the devicetree spec. Or just use >> > cache-controller for the node name. >> >> This was as per discussion in [1][2] where dt-schema throws an error >> since it expects cache-level to be associated with cache-controller. >> > > Ah right. Can you add system-cache-controller to the dt spec? Sure, I'll add it. Hopefully that won't have to block this change? Because I might need some time to get permissions to add it there. Thanks, Sai
Quoting Sai Prakash Ranjan (2021-02-27 05:58:25) > On 2021-02-27 00:15, Stephen Boyd wrote: > > Quoting Sai Prakash Ranjan (2021-02-26 00:04:27) > >> On 2021-02-26 01:07, Stephen Boyd wrote: > >> > Quoting Sai Prakash Ranjan (2021-02-25 01:30:19) > >> >> Add a DT node for Last level cache (aka. system cache) > >> >> controller which provides control over the last level > >> >> cache present on SC7280 SoC. > >> >> > >> >> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > >> >> --- > >> > > >> > Reviewed-by: Stephen Boyd <swboyd@chromium.org> > >> > > >> > Should add system-cache-controller to the devicetree spec. Or just use > >> > cache-controller for the node name. > >> > >> This was as per discussion in [1][2] where dt-schema throws an error > >> since it expects cache-level to be associated with cache-controller. > >> > > > > Ah right. Can you add system-cache-controller to the dt spec? > > Sure, I'll add it. Hopefully that won't have to block this change? > Because I might need some time to get permissions to add it there. > Doesn't block it for me.
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 3b86052b78bc..aeeb47c70c3a 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -338,6 +338,13 @@ uart5: serial@994000 { }; }; + system-cache-controller@9200000 { + compatible = "qcom,sc7280-llcc"; + reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc7280-pdc", "qcom,pdc"; reg = <0 0xb220000 0 0x30000>;
Add a DT node for Last level cache (aka. system cache) controller which provides control over the last level cache present on SC7280 SoC. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)