[v3,1/2] pinctrl: qcom: sc8180x: drop the use of tiles

To support both ACPI and DT, it makes more sense to not use tiles for
pinctrl-sc8180x driver, as ACPI table describes TLMM block with one
single memory resource.  Since DTS of SC8180X hasn't landed, there is
still chance to align DT description with ACPI.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

---
 drivers/pinctrl/qcom/pinctrl-sc8180x.c | 41 +++++++++-----------------
 1 file changed, 14 insertions(+), 27 deletions(-)

-- 
2.17.1

On Thu 04 Mar 00:05 CST 2021, Shawn Guo wrote:

> To support both ACPI and DT, it makes more sense to not use tiles for
> pinctrl-sc8180x driver, as ACPI table describes TLMM block with one
> single memory resource.  Since DTS of SC8180X hasn't landed, there is
> still chance to align DT description with ACPI.
> 

I don't like the idea that we make up addresses to put in the DT to fit
what was put in the DSDT. It is 3 different memory regions, with things
in-between that Linux shouldn't touch.

Isn't it possible to during ACPI probe take reg 0 and register the 3
named regions instead?

Regards,
Bjorn

> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
>  drivers/pinctrl/qcom/pinctrl-sc8180x.c | 41 +++++++++-----------------
>  1 file changed, 14 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/pinctrl/qcom/pinctrl-sc8180x.c b/drivers/pinctrl/qcom/pinctrl-sc8180x.c
> index b765bf667574..66f76ed22200 100644
> --- a/drivers/pinctrl/qcom/pinctrl-sc8180x.c
> +++ b/drivers/pinctrl/qcom/pinctrl-sc8180x.c
> @@ -11,17 +11,9 @@
>  
>  #include "pinctrl-msm.h"
>  
> -static const char * const sc8180x_tiles[] = {
> -	"south",
> -	"east",
> -	"west"
> -};
> -
> -enum {
> -	SOUTH,
> -	EAST,
> -	WEST
> -};
> +#define WEST	0x00100000
> +#define EAST	0x00500000
> +#define SOUTH	0x00d00000
>  
>  #define FUNCTION(fname)					\
>  	[msm_mux_##fname] = {				\
> @@ -31,7 +23,7 @@ enum {
>  	}
>  
>  #define REG_SIZE 0x1000
> -#define PINGROUP_OFFSET(id, _tile, offset, f1, f2, f3, f4, f5, f6, f7, f8, f9)	\
> +#define PINGROUP_OFFSET(id, base, offset, f1, f2, f3, f4, f5, f6, f7, f8, f9)	\
>  	{						\
>  		.name = "gpio" #id,			\
>  		.pins = gpio##id##_pins,		\
> @@ -49,12 +41,11 @@ enum {
>  			msm_mux_##f9			\
>  		},					\
>  		.nfuncs = 10,				\
> -		.ctl_reg = REG_SIZE * id + offset,	\
> -		.io_reg = REG_SIZE * id + 0x4 + offset,	\
> -		.intr_cfg_reg = REG_SIZE * id + 0x8 + offset,	\
> -		.intr_status_reg = REG_SIZE * id + 0xc + offset,\
> -		.intr_target_reg = REG_SIZE * id + 0x8 + offset,\
> -		.tile = _tile,				\
> +		.ctl_reg = base + REG_SIZE * id + offset,		\
> +		.io_reg = base + REG_SIZE * id + 0x4 + offset,		\
> +		.intr_cfg_reg = base + REG_SIZE * id + 0x8 + offset,	\
> +		.intr_status_reg = base + REG_SIZE * id + 0xc + offset,	\
> +		.intr_target_reg = base + REG_SIZE * id + 0x8 + offset,	\
>  		.mux_bit = 2,				\
>  		.pull_bit = 0,				\
>  		.drv_bit = 6,				\
> @@ -71,20 +62,19 @@ enum {
>  		.intr_detection_width = 2,		\
>  	}
>  
> -#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9)	\
> -	PINGROUP_OFFSET(id, _tile, 0x0, f1, f2, f3, f4, f5, f6, f7, f8, f9)
> +#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9)	\
> +	PINGROUP_OFFSET(id, base, 0x0, f1, f2, f3, f4, f5, f6, f7, f8, f9)
>  
>  #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv)	\
>  	{						\
>  		.name = #pg_name,			\
>  		.pins = pg_name##_pins,			\
>  		.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins),	\
> -		.ctl_reg = ctl,				\
> +		.ctl_reg = EAST + ctl,			\
>  		.io_reg = 0,				\
>  		.intr_cfg_reg = 0,			\
>  		.intr_status_reg = 0,			\
>  		.intr_target_reg = 0,			\
> -		.tile = EAST,				\
>  		.mux_bit = -1,				\
>  		.pull_bit = pull,			\
>  		.drv_bit = drv,				\
> @@ -105,12 +95,11 @@ enum {
>  		.name = #pg_name,			\
>  		.pins = pg_name##_pins,			\
>  		.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins),	\
> -		.ctl_reg = 0xb6000,			\
> -		.io_reg = 0xb6004,			\
> +		.ctl_reg = SOUTH + 0xb6000,		\
> +		.io_reg = SOUTH + 0xb6004,		\
>  		.intr_cfg_reg = 0,			\
>  		.intr_status_reg = 0,			\
>  		.intr_target_reg = 0,			\
> -		.tile = SOUTH,				\
>  		.mux_bit = -1,				\
>  		.pull_bit = 3,				\
>  		.drv_bit = 0,				\
> @@ -1575,8 +1564,6 @@ static const struct msm_gpio_wakeirq_map sc8180x_pdc_map[] = {
>  };
>  
>  static struct msm_pinctrl_soc_data sc8180x_pinctrl = {
> -	.tiles = sc8180x_tiles,
> -	.ntiles = ARRAY_SIZE(sc8180x_tiles),
>  	.pins = sc8180x_pins,
>  	.npins = ARRAY_SIZE(sc8180x_pins),
>  	.functions = sc8180x_functions,
> -- 
> 2.17.1
>

On Mon, Mar 08, 2021 at 07:08:00PM -0600, Bjorn Andersson wrote:
> On Thu 04 Mar 00:05 CST 2021, Shawn Guo wrote:

> 

> > To support both ACPI and DT, it makes more sense to not use tiles for

> > pinctrl-sc8180x driver, as ACPI table describes TLMM block with one

> > single memory resource.  Since DTS of SC8180X hasn't landed, there is

> > still chance to align DT description with ACPI.

> > 

> 

> I don't like the idea that we make up addresses to put in the DT to fit

> what was put in the DSDT. It is 3 different memory regions, with things

> in-between that Linux shouldn't touch.


This is not a new idea but something pinctrl-sdm845 has been doing for
years.  And IMHO, it's not a bad idea but a reasonable compromise.

> Isn't it possible to during ACPI probe take reg 0 and register the 3

> named regions instead?


It is possible.  But let's see what it takes.  We will need to have some
quirk handling in the ACPI core to detect TLMM device on Flex 5G
machine, and then override the memory resource registration for that
device.  Myself is not even convinced this is a good solution, not
mentioning whether ACPI maintainers will accept it.

Shawn

On Mon 08 Mar 20:56 CST 2021, Shawn Guo wrote:

> On Mon, Mar 08, 2021 at 07:08:00PM -0600, Bjorn Andersson wrote:

> > On Thu 04 Mar 00:05 CST 2021, Shawn Guo wrote:

> > 

> > > To support both ACPI and DT, it makes more sense to not use tiles for

> > > pinctrl-sc8180x driver, as ACPI table describes TLMM block with one

> > > single memory resource.  Since DTS of SC8180X hasn't landed, there is

> > > still chance to align DT description with ACPI.

> > > 

> > 

> > I don't like the idea that we make up addresses to put in the DT to fit

> > what was put in the DSDT. It is 3 different memory regions, with things

> > in-between that Linux shouldn't touch.

> 

> This is not a new idea but something pinctrl-sdm845 has been doing for

> years.  And IMHO, it's not a bad idea but a reasonable compromise.

> 


SDM845 was the first platform where the previous contiguous TLMM block
was split up in tiles, at the time we didn't see a need to split it up.

But then we hit QCS404 (iirc) where one of the tiles was way off and
concluded that we needed the DT binding to actually represent the
hardware - so the tiles concept was introduced.

Unfortunately introducing the tiles back into sdm845 would cause issues
with existing DT, so that has not happened.

> > Isn't it possible to during ACPI probe take reg 0 and register the 3

> > named regions instead?

> 

> It is possible.  But let's see what it takes.  We will need to have some

> quirk handling in the ACPI core to detect TLMM device on Flex 5G

> machine, and then override the memory resource registration for that

> device.  Myself is not even convinced this is a good solution, not

> mentioning whether ACPI maintainers will accept it.

> 


I don't think this quirk should belong in the core. Can't you massage
the resources once you're in the probe function in pinctrl-sc8180x.c? Or
the platform resources can't be modified when we reach that point?

Regards,
Bjorn

On Mon, Mar 08, 2021 at 09:42:43PM -0600, Bjorn Andersson wrote:
> On Mon 08 Mar 20:56 CST 2021, Shawn Guo wrote:

> 

> > On Mon, Mar 08, 2021 at 07:08:00PM -0600, Bjorn Andersson wrote:

> > > On Thu 04 Mar 00:05 CST 2021, Shawn Guo wrote:

> > > 

> > > > To support both ACPI and DT, it makes more sense to not use tiles for

> > > > pinctrl-sc8180x driver, as ACPI table describes TLMM block with one

> > > > single memory resource.  Since DTS of SC8180X hasn't landed, there is

> > > > still chance to align DT description with ACPI.

> > > > 

> > > 

> > > I don't like the idea that we make up addresses to put in the DT to fit

> > > what was put in the DSDT. It is 3 different memory regions, with things

> > > in-between that Linux shouldn't touch.

> > 

> > This is not a new idea but something pinctrl-sdm845 has been doing for

> > years.  And IMHO, it's not a bad idea but a reasonable compromise.

> > 

> 

> SDM845 was the first platform where the previous contiguous TLMM block

> was split up in tiles, at the time we didn't see a need to split it up.

> 

> But then we hit QCS404 (iirc) where one of the tiles was way off and

> concluded that we needed the DT binding to actually represent the

> hardware - so the tiles concept was introduced.

> 

> Unfortunately introducing the tiles back into sdm845 would cause issues

> with existing DT, so that has not happened.

> 

> > > Isn't it possible to during ACPI probe take reg 0 and register the 3

> > > named regions instead?

> > 

> > It is possible.  But let's see what it takes.  We will need to have some

> > quirk handling in the ACPI core to detect TLMM device on Flex 5G

> > machine, and then override the memory resource registration for that

> > device.  Myself is not even convinced this is a good solution, not

> > mentioning whether ACPI maintainers will accept it.

> > 

> 

> I don't think this quirk should belong in the core. Can't you massage

> the resources once you're in the probe function in pinctrl-sc8180x.c? Or

> the platform resources can't be modified when we reach that point?


Okay, I misread your comment.  Yes, we can massage the resources, but
it's a bit tricky.  It took me hours get it right.  Anyway, I will send
it out for review.  Hopefully we can agree on one solution out of three
I have worked out.

Shawn