| Message ID | 20210303113952.178519-11-benjamin.gaignard@collabora.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add HANTRO G2/HEVC decoder support for IMX8MQ | expand |
On Wed, 03 Mar 2021 12:39:51 +0100, Benjamin Gaignard wrote: > The current bindings seem to make the assumption that the > two VPUs hardware blocks (G1 and G2) are only one set of > registers. > After implementing the VPU reset driver and G2 decoder driver > it shows that all the VPUs are independent and don't need to > know about the registers of the other blocks. > Remove from the bindings the need to set all blocks register > but keep reg-names property because removing it from the driver > may affect other variants. > > Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> > --- > version 4: > - rebase the change on top of VPU reset patches: > https://www.spinics.net/lists/arm-kernel/msg878440.html > > version 2: > - be more verbose about why I change the bindings > Keep in mind that series comes after: https://www.spinics.net/lists/arm-kernel/msg875766.html > without that review and ack it won't work > > .../bindings/media/nxp,imx8mq-vpu.yaml | 46 ++++++++++++------- > 1 file changed, 30 insertions(+), 16 deletions(-) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml index fd53a4e43572..468435c70eef 100644 --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml @@ -15,23 +15,25 @@ description: properties: compatible: - const: nxp,imx8mq-vpu + enum: + - nxp,imx8mq-vpu + - nxp,imx8mq-vpu-g2 reg: - maxItems: 2 + maxItems: 1 reg-names: - items: - - const: g1 - - const: g2 + enum: + - g1 + - g2 interrupts: - maxItems: 2 + maxItems: 1 interrupt-names: - items: - - const: g1 - - const: g2 + enum: + - g1 + - g2 clocks: maxItems: 3 @@ -66,14 +68,12 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/reset/imx8mq-vpu-reset.h> - vpu: video-codec@38300000 { + vpu_g1: video-codec@38300000 { compatible = "nxp,imx8mq-vpu"; - reg = <0x38300000 0x10000>, - <0x38310000 0x10000>; - reg-names = "g1", "g2"; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "g1", "g2"; + reg = <0x38300000 0x10000>; + reg-names = "g1"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "g1"; clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, <&clk IMX8MQ_CLK_VPU_G2_ROOT>, <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; @@ -81,3 +81,17 @@ examples: power-domains = <&pgc_vpu>; resets = <&vpu_reset IMX8MQ_RESET_VPU_RESET_G1>; }; + + vpu_g2: video-codec@38310000 { + compatible = "nxp,imx8mq-vpu-g2"; + reg = <0x38310000 0x10000>; + reg-names = "g2"; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "g2"; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, + <&clk IMX8MQ_CLK_VPU_G2_ROOT>, + <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; + clock-names = "g1", "g2", "bus"; + power-domains = <&pgc_vpu>; + resets = <&vpu_reset IMX8MQ_RESET_VPU_RESET_G2>; + };
The current bindings seem to make the assumption that the two VPUs hardware blocks (G1 and G2) are only one set of registers. After implementing the VPU reset driver and G2 decoder driver it shows that all the VPUs are independent and don't need to know about the registers of the other blocks. Remove from the bindings the need to set all blocks register but keep reg-names property because removing it from the driver may affect other variants. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> --- version 4: - rebase the change on top of VPU reset patches: https://www.spinics.net/lists/arm-kernel/msg878440.html version 2: - be more verbose about why I change the bindings Keep in mind that series comes after: https://www.spinics.net/lists/arm-kernel/msg875766.html without that review and ack it won't work .../bindings/media/nxp,imx8mq-vpu.yaml | 46 ++++++++++++------- 1 file changed, 30 insertions(+), 16 deletions(-)