diff mbox series

[v3] dt-bindings: clk: zynqmp: convert bindings to YAML

Message ID 20210613204742.292053-1-iwamatsu@nigauri.org
State New
Headers show
Series [v3] dt-bindings: clk: zynqmp: convert bindings to YAML | expand

Commit Message

Nobuhiro Iwamatsu June 13, 2021, 8:47 p.m. UTC 
Convert common clock for Xilinx Zynq MPSoC SoC bindings documentation
to YAML.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
v3: Drop commit for mailbox/xlnx,zynqmp-ipi-mailbox.txt
v2: Fix warning with DT_CHECKER_FLAGS=-m.

 .../bindings/clock/xlnx,zynqmp-clk.txt        | 63 -------------------
 .../bindings/clock/xlnx,zynqmp-clk.yaml       | 63 +++++++++++++++++++
 2 files changed, 63 insertions(+), 63 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt
 create mode 100644 Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml

Comments

Rob Herring (Arm) June 24, 2021, 8:25 p.m. UTC | #1 
On Mon, Jun 14, 2021 at 05:47:42AM +0900, Nobuhiro Iwamatsu wrote:
> Convert common clock for Xilinx Zynq MPSoC SoC bindings documentation

> to YAML.

> 

> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

> ---

> v3: Drop commit for mailbox/xlnx,zynqmp-ipi-mailbox.txt

> v2: Fix warning with DT_CHECKER_FLAGS=-m.

> 

>  .../bindings/clock/xlnx,zynqmp-clk.txt        | 63 -------------------

>  .../bindings/clock/xlnx,zynqmp-clk.yaml       | 63 +++++++++++++++++++

>  2 files changed, 63 insertions(+), 63 deletions(-)

>  delete mode 100644 Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt

>  create mode 100644 Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml

> 

> diff --git a/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt b/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt

> deleted file mode 100644

> index 391ee1a60bed4a..00000000000000

> --- a/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt

> +++ /dev/null

> @@ -1,63 +0,0 @@

> ---------------------------------------------------------------------------

> -Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using

> -Zynq MPSoC firmware interface

> ---------------------------------------------------------------------------

> -The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock

> -tree. It reads required input clock frequencies from the devicetree and acts

> -as clock provider for all clock consumers of PS clocks.

> -

> -See clock_bindings.txt for more information on the generic clock bindings.

> -

> -Required properties:

> - - #clock-cells:	Must be 1

> - - compatible:		Must contain:	"xlnx,zynqmp-clk"

> - - clocks:		List of clock specifiers which are external input

> -			clocks to the given clock controller. Please refer

> -			the next section to find the input clocks for a

> -			given controller.

> - - clock-names:		List of clock names which are exteral input clocks

> -			to the given clock controller. Please refer to the

> -			clock bindings for more details.

> -

> -Input clocks for zynqmp Ultrascale+ clock controller:

> -

> -The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock

> -inputs. These required clock inputs are:

> - - pss_ref_clk (PS reference clock)

> - - video_clk (reference clock for video system )

> - - pss_alt_ref_clk (alternative PS reference clock)

> - - aux_ref_clk

> - - gt_crx_ref_clk (transceiver reference clock)

> -

> -The following strings are optional parameters to the 'clock-names' property in

> -order to provide an optional (E)MIO clock source:

> - - swdt0_ext_clk

> - - swdt1_ext_clk

> - - gem0_emio_clk

> - - gem1_emio_clk

> - - gem2_emio_clk

> - - gem3_emio_clk

> - - mio_clk_XX		# with XX = 00..77

> - - mio_clk_50_or_51	#for the mux clock to gem tsu from 50 or 51


What happened to these with no explanation.

> -

> -

> -Output clocks are registered based on clock information received

> -from firmware. Output clocks indexes are mentioned in

> -include/dt-bindings/clock/xlnx-zynqmp-clk.h.

> -

> --------

> -Example

> --------

> -

> -firmware {

> -	zynqmp_firmware: zynqmp-firmware {

> -		compatible = "xlnx,zynqmp-firmware";

> -		method = "smc";

> -		zynqmp_clk: clock-controller {

> -			#clock-cells = <1>;

> -			compatible = "xlnx,zynqmp-clk";

> -			clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;

> -			clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";

> -		};

> -	};

> -};

> diff --git a/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml

> new file mode 100644

> index 00000000000000..e7a1384fb646e4

> --- /dev/null

> +++ b/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml

> @@ -0,0 +1,63 @@

> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

> +%YAML 1.2

> +---

> +$id: http://devicetree.org/schemas/clock/xlnx,zynqmp-clk.yaml#

> +$schema: http://devicetree.org/meta-schemas/core.yaml#

> +

> +title: Xilinx Zynq Ultrascale+ MPSoC clock controller Device Tree Bindings

> +

> +maintainers:

> +  - Michal Simek <michal.simek@xilinx.com>

> +

> +description: |

> +  The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock

> +  tree. It reads required input clock frequencies from the devicetree and acts

> +  as clock provider for all clock consumers of PS clocks.

> +

> +properties:

> +  compatible:

> +    const: xlnx,zynqmp-clk

> +

> +  "#clock-cells":

> +    const: 1

> +

> +  clocks:

> +    description: |

> +      List of clock specifiers which are external input

> +      clocks to the given clock controller.

> +    items:

> +      - description: PS reference clock

> +      - description: reference clock for video system

> +      - description: alternative PS reference clock

> +      - description: auxiliary reference clock

> +      - description: transceiver reference clock

> +

> +  clock-names:

> +    items:

> +      - const: pss_ref_clk

> +      - const: video_clk

> +      - const: pss_alt_ref_clk

> +      - const: aux_ref_clk

> +      - const: gt_crx_ref_clk

> +

> +required:

> +  - compatible

> +  - "#clock-cells"

> +  - clocks

> +  - clock-names

> +

> +additionalProperties: false

> +

> +examples:

> +  - |

> +    firmware {

> +      zynqmp_firmware: zynqmp-firmware {

> +        zynqmp_clk: clock-controller {

> +          #clock-cells = <1>;

> +          compatible = "xlnx,zynqmp-clk";

> +          clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;

> +          clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";

> +        };

> +      };

> +    };

> +...

> -- 

> 2.32.0

> 

>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt b/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt
deleted file mode 100644
index 391ee1a60bed4a..00000000000000
--- a/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt
+++ /dev/null
@@ -1,63 +0,0 @@ 
---------------------------------------------------------------------------
-Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
-Zynq MPSoC firmware interface
---------------------------------------------------------------------------
-The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
-tree. It reads required input clock frequencies from the devicetree and acts
-as clock provider for all clock consumers of PS clocks.
-
-See clock_bindings.txt for more information on the generic clock bindings.
-
-Required properties:
- - #clock-cells:	Must be 1
- - compatible:		Must contain:	"xlnx,zynqmp-clk"
- - clocks:		List of clock specifiers which are external input
-			clocks to the given clock controller. Please refer
-			the next section to find the input clocks for a
-			given controller.
- - clock-names:		List of clock names which are exteral input clocks
-			to the given clock controller. Please refer to the
-			clock bindings for more details.
-
-Input clocks for zynqmp Ultrascale+ clock controller:
-
-The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
-inputs. These required clock inputs are:
- - pss_ref_clk (PS reference clock)
- - video_clk (reference clock for video system )
- - pss_alt_ref_clk (alternative PS reference clock)
- - aux_ref_clk
- - gt_crx_ref_clk (transceiver reference clock)
-
-The following strings are optional parameters to the 'clock-names' property in
-order to provide an optional (E)MIO clock source:
- - swdt0_ext_clk
- - swdt1_ext_clk
- - gem0_emio_clk
- - gem1_emio_clk
- - gem2_emio_clk
- - gem3_emio_clk
- - mio_clk_XX		# with XX = 00..77
- - mio_clk_50_or_51	#for the mux clock to gem tsu from 50 or 51
-
-
-Output clocks are registered based on clock information received
-from firmware. Output clocks indexes are mentioned in
-include/dt-bindings/clock/xlnx-zynqmp-clk.h.
-
--------
-Example
--------
-
-firmware {
-	zynqmp_firmware: zynqmp-firmware {
-		compatible = "xlnx,zynqmp-firmware";
-		method = "smc";
-		zynqmp_clk: clock-controller {
-			#clock-cells = <1>;
-			compatible = "xlnx,zynqmp-clk";
-			clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;
-			clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
-		};
-	};
-};
diff --git a/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml
new file mode 100644
index 00000000000000..e7a1384fb646e4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml
@@ -0,0 +1,63 @@ 
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/xlnx,zynqmp-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Zynq Ultrascale+ MPSoC clock controller Device Tree Bindings
+
+maintainers:
+  - Michal Simek <michal.simek@xilinx.com>
+
+description: |
+  The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
+  tree. It reads required input clock frequencies from the devicetree and acts
+  as clock provider for all clock consumers of PS clocks.
+
+properties:
+  compatible:
+    const: xlnx,zynqmp-clk
+
+  "#clock-cells":
+    const: 1
+
+  clocks:
+    description: |
+      List of clock specifiers which are external input
+      clocks to the given clock controller.
+    items:
+      - description: PS reference clock
+      - description: reference clock for video system
+      - description: alternative PS reference clock
+      - description: auxiliary reference clock
+      - description: transceiver reference clock
+
+  clock-names:
+    items:
+      - const: pss_ref_clk
+      - const: video_clk
+      - const: pss_alt_ref_clk
+      - const: aux_ref_clk
+      - const: gt_crx_ref_clk
+
+required:
+  - compatible
+  - "#clock-cells"
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    firmware {
+      zynqmp_firmware: zynqmp-firmware {
+        zynqmp_clk: clock-controller {
+          #clock-cells = <1>;
+          compatible = "xlnx,zynqmp-clk";
+          clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;
+          clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
+        };
+      };
+    };
+...