| Message ID | 20210624025647.101387-1-reniuschengl@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | mmc: sdhci-pci-gli: Finetune GL9763E L1 Entry Delay | expand |
On 24/06/21 5:56 am, Renius Chen wrote: > Finetune the L1 entry delay to 20us for better balance of performance and > battery life. > > Signed-off-by: Renius Chen <reniuschengl@gmail.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> > --- > drivers/mmc/host/sdhci-pci-gli.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c > index 302a7579a9b3..4e3c0561354d 100644 > --- a/drivers/mmc/host/sdhci-pci-gli.c > +++ b/drivers/mmc/host/sdhci-pci-gli.c > @@ -90,7 +90,7 @@ > > #define PCIE_GLI_9763E_CFG2 0x8A4 > #define GLI_9763E_CFG2_L1DLY GENMASK(28, 19) > -#define GLI_9763E_CFG2_L1DLY_MID 0x54 > +#define GLI_9763E_CFG2_L1DLY_MID 0x50 > > #define PCIE_GLI_9763E_MMC_CTRL 0x960 > #define GLI_9763E_HS400_SLOW BIT(3) > @@ -810,7 +810,7 @@ static void gli_set_gl9763e(struct sdhci_pci_slot *slot) > > pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value); > value &= ~GLI_9763E_CFG2_L1DLY; > - /* set ASPM L1 entry delay to 21us */ > + /* set ASPM L1 entry delay to 20us */ > value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID); > pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value); > >
On Thu, 24 Jun 2021 at 04:56, Renius Chen <reniuschengl@gmail.com> wrote: > > Finetune the L1 entry delay to 20us for better balance of performance and > battery life. > > Signed-off-by: Renius Chen <reniuschengl@gmail.com> > --- > drivers/mmc/host/sdhci-pci-gli.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c > index 302a7579a9b3..4e3c0561354d 100644 > --- a/drivers/mmc/host/sdhci-pci-gli.c > +++ b/drivers/mmc/host/sdhci-pci-gli.c > @@ -90,7 +90,7 @@ > > #define PCIE_GLI_9763E_CFG2 0x8A4 > #define GLI_9763E_CFG2_L1DLY GENMASK(28, 19) > -#define GLI_9763E_CFG2_L1DLY_MID 0x54 > +#define GLI_9763E_CFG2_L1DLY_MID 0x50 We just changed from 21us to 20us. Really, how big of a difference can this make? Moreover, I suppose the difference is related to the running use case. No? If you really want this, at least I want an ack from Ben for it, then let's be done with it. Kind regards Uffe > > #define PCIE_GLI_9763E_MMC_CTRL 0x960 > #define GLI_9763E_HS400_SLOW BIT(3) > @@ -810,7 +810,7 @@ static void gli_set_gl9763e(struct sdhci_pci_slot *slot) > > pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value); > value &= ~GLI_9763E_CFG2_L1DLY; > - /* set ASPM L1 entry delay to 21us */ > + /* set ASPM L1 entry delay to 20us */ > value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID); > pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value); > > -- > 2.27.0 >
Ulf Hansson <ulf.hansson@linaro.org> 於 2021年6月30日 週三 下午11:16寫道： > > On Thu, 24 Jun 2021 at 04:56, Renius Chen <reniuschengl@gmail.com> wrote: > > > > Finetune the L1 entry delay to 20us for better balance of performance and > > battery life. > > > > Signed-off-by: Renius Chen <reniuschengl@gmail.com> > > --- > > drivers/mmc/host/sdhci-pci-gli.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c > > index 302a7579a9b3..4e3c0561354d 100644 > > --- a/drivers/mmc/host/sdhci-pci-gli.c > > +++ b/drivers/mmc/host/sdhci-pci-gli.c > > @@ -90,7 +90,7 @@ > > > > #define PCIE_GLI_9763E_CFG2 0x8A4 > > #define GLI_9763E_CFG2_L1DLY GENMASK(28, 19) > > -#define GLI_9763E_CFG2_L1DLY_MID 0x54 > > +#define GLI_9763E_CFG2_L1DLY_MID 0x50 > > We just changed from 21us to 20us. Really, how big of a difference can > this make? > > Moreover, I suppose the difference is related to the running use case. No? > > If you really want this, at least I want an ack from Ben for it, then > let's be done with it. > > Kind regards > Uffe > Yes, according to the result of our customer's PLT test for battery life, It will pass the test with 20us and will not pass the test with 21us. I'll ask Ben for acking this, thank you. > > > > #define PCIE_GLI_9763E_MMC_CTRL 0x960 > > #define GLI_9763E_HS400_SLOW BIT(3) > > @@ -810,7 +810,7 @@ static void gli_set_gl9763e(struct sdhci_pci_slot *slot) > > > > pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value); > > value &= ~GLI_9763E_CFG2_L1DLY; > > - /* set ASPM L1 entry delay to 21us */ > > + /* set ASPM L1 entry delay to 20us */ > > value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID); > > pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value); > > > > -- > > 2.27.0 > >
Hi Ulf and Renius, > Ulf Hansson <ulf.hansson@linaro.org> 於 2021年6月30日 週三 下午11:16寫道： > > > > On Thu, 24 Jun 2021 at 04:56, Renius Chen <reniuschengl@gmail.com> wrote: > > > > > > Finetune the L1 entry delay to 20us for better balance of performance and > > > battery life. > > > > > > Signed-off-by: Renius Chen <reniuschengl@gmail.com> > > > --- > > > drivers/mmc/host/sdhci-pci-gli.c | 4 ++-- > > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c > > > index 302a7579a9b3..4e3c0561354d 100644 > > > --- a/drivers/mmc/host/sdhci-pci-gli.c > > > +++ b/drivers/mmc/host/sdhci-pci-gli.c > > > @@ -90,7 +90,7 @@ > > > > > > #define PCIE_GLI_9763E_CFG2 0x8A4 > > > #define GLI_9763E_CFG2_L1DLY GENMASK(28, 19) > > > -#define GLI_9763E_CFG2_L1DLY_MID 0x54 > > > +#define GLI_9763E_CFG2_L1DLY_MID 0x50 > > > > We just changed from 21us to 20us. Really, how big of a difference can > > this make? > > > > Moreover, I suppose the difference is related to the running use case. No? > > > > If you really want this, at least I want an ack from Ben for it, then > > let's be done with it. > > > > Kind regards > > Uffe > > > Yes, according to the result of our customer's PLT test for battery life, > It will pass the test with 20us and will not pass the test with 21us. > I'll ask Ben for acking this, thank you. Using 20us can pass the battery life testing, but need to consider that it may reduce some performance. So this patch should be together with 4k patch or after 4k patch. Then I can acked Acked-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>. Best regards, Ben > > > > > > > #define PCIE_GLI_9763E_MMC_CTRL 0x960 > > > #define GLI_9763E_HS400_SLOW BIT(3) > > > @@ -810,7 +810,7 @@ static void gli_set_gl9763e(struct sdhci_pci_slot *slot) > > > > > > pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value); > > > value &= ~GLI_9763E_CFG2_L1DLY; > > > - /* set ASPM L1 entry delay to 21us */ > > > + /* set ASPM L1 entry delay to 20us */ > > > value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID); > > > pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value); > > > > > > -- > > > 2.27.0 > > >
diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c index 302a7579a9b3..4e3c0561354d 100644 --- a/drivers/mmc/host/sdhci-pci-gli.c +++ b/drivers/mmc/host/sdhci-pci-gli.c @@ -90,7 +90,7 @@ #define PCIE_GLI_9763E_CFG2 0x8A4 #define GLI_9763E_CFG2_L1DLY GENMASK(28, 19) -#define GLI_9763E_CFG2_L1DLY_MID 0x54 +#define GLI_9763E_CFG2_L1DLY_MID 0x50 #define PCIE_GLI_9763E_MMC_CTRL 0x960 #define GLI_9763E_HS400_SLOW BIT(3) @@ -810,7 +810,7 @@ static void gli_set_gl9763e(struct sdhci_pci_slot *slot) pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value); value &= ~GLI_9763E_CFG2_L1DLY; - /* set ASPM L1 entry delay to 21us */ + /* set ASPM L1 entry delay to 20us */ value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID); pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value);
Finetune the L1 entry delay to 20us for better balance of performance and battery life. Signed-off-by: Renius Chen <reniuschengl@gmail.com> --- drivers/mmc/host/sdhci-pci-gli.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)