@@ -336,5 +336,35 @@
resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
};
};
+
+ mmc0: sdhci@09060000 {
+ compatible = "st,sdhci-stih407", "st,sdhci";
+ status = "disabled";
+ reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
+ reg-names = "mmc", "top-mmc-delay";
+ interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
+ interrupt-names = "mmcirq";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mmc0>;
+ clock-names = "mmc";
+ clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
+ bus-width = <8>;
+ non-removable;
+ };
+
+ mmc1: sdhci@09080000 {
+ compatible = "st,sdhci-stih407", "st,sdhci";
+ status = "disabled";
+ reg = <0x09080000 0x7ff>;
+ reg-names = "mmc";
+ interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
+ interrupt-names = "mmcirq";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sd1>;
+ clock-names = "mmc";
+ clocks = <&clk_s_c0_flexgen CLK_MMC_1>;
+ resets = <&softreset STIH407_MMC1_SOFTRESET>;
+ bus-width = <4>;
+ };
};
};
@@ -26,4 +26,14 @@
aliases {
ttyAS0 = &sbc_serial0;
};
+
+ soc {
+
+ mmc0: sdhci@09060000 {
+ max-frequency = <200000000>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ sd-uhs-ddr50;
+ };
+ };
};
@@ -47,6 +47,14 @@
status = "okay";
};
+ mmc0: sdhci@09060000 {
+ status = "okay";
+ };
+
+ mmc1: sdhci@09080000 {
+ status = "okay";
+ };
+
/* SSC11 to HDMI */
hdmiddc: i2c@9541000 {
status = "okay";
The nodes have been split to allow as much commonality as possible. The stih407 has a silicon bug with eMMC UHS modes (with top regs) and as such doesn't have any of the uhs dt properties. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> --- arch/arm/boot/dts/stih407-family.dtsi | 30 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/stih410-b2120.dts | 10 ++++++++++ arch/arm/boot/dts/stihxxx-b2120.dtsi | 8 ++++++++ 3 files changed, 48 insertions(+)