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[RFC,2/4] arm64: dts: rockchip: split rk3568 device tree

Message ID 20210710151034.32857-3-pgwipeout@gmail.com
State New
Headers show
Series split rk3568 and rk3566 device trees | expand

Commit Message

Peter Geis July 10, 2021, 3:10 p.m. UTC 
In preparation for the rk3566 inclusion, split apart the rk3568 specific
nodes into a separate device tree.
This allows us to create the rk3566 device tree without deleting nodes.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3568.dtsi | 48 ++++++++++++++++++++++++
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 36 ------------------
 2 files changed, 48 insertions(+), 36 deletions(-)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3568.dtsi
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
new file mode 100644
index 000000000000..da01a59f6f26
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -0,0 +1,48 @@ 
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include "rk356x.dtsi"
+
+/ {
+	compatible = "rockchip,rk3568";
+
+	qos_pcie3x1: qos@fe190080 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x0 0xfe190080 0x0 0x20>;
+	};
+
+	qos_pcie3x2: qos@fe190100 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x0 0xfe190100 0x0 0x20>;
+	};
+
+	qos_sata0: qos@fe190200 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x0 0xfe190200 0x0 0x20>;
+	};
+};
+
+&cpu0_opp_table {
+	opp-1992000000 {
+		opp-hz = /bits/ 64 <1992000000>;
+		opp-microvolt = <1150000 1150000 1150000>;
+	};
+};
+
+&power {
+	power-domain@RK3568_PD_PIPE {
+		reg = <RK3568_PD_PIPE>;
+		clocks = <&cru PCLK_PIPE>;
+		pm_qos = <&qos_pcie2x1>,
+			 <&qos_pcie3x1>,
+			 <&qos_pcie3x2>,
+			 <&qos_sata0>,
+			 <&qos_sata1>,
+			 <&qos_sata2>,
+			 <&qos_usb3_0>,
+			 <&qos_usb3_1>;
+		#power-domain-cells = <0>;
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 2737f26775ff..fb4ae22b827a 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -13,8 +13,6 @@ 
 #include <dt-bindings/thermal/thermal.h>
 
 / {
-	compatible = "rockchip,rk3568";
-
 	interrupt-parent = <&gic>;
 	#address-cells = <2>;
 	#size-cells = <2>;
@@ -121,11 +119,6 @@  opp-1800000000 {
 			opp-hz = /bits/ 64 <1800000000>;
 			opp-microvolt = <1050000 1050000 1150000>;
 		};
-
-		opp-1992000000 {
-			opp-hz = /bits/ 64 <1992000000>;
-			opp-microvolt = <1150000 1150000 1150000>;
-		};
 	};
 
 	firmware {
@@ -334,20 +327,6 @@  power-domain@RK3568_PD_RKVENC {
 					 <&qos_rkvenc_wr_m0>;
 				#power-domain-cells = <0>;
 			};
-
-			power-domain@RK3568_PD_PIPE {
-				reg = <RK3568_PD_PIPE>;
-				clocks = <&cru PCLK_PIPE>;
-				pm_qos = <&qos_pcie2x1>,
-					 <&qos_pcie3x1>,
-					 <&qos_pcie3x2>,
-					 <&qos_sata0>,
-					 <&qos_sata1>,
-					 <&qos_sata2>,
-					 <&qos_usb3_0>,
-					 <&qos_usb3_1>;
-				#power-domain-cells = <0>;
-			};
 		};
 	};
 
@@ -431,21 +410,6 @@  qos_pcie2x1: qos@fe190000 {
 		reg = <0x0 0xfe190000 0x0 0x20>;
 	};
 
-	qos_pcie3x1: qos@fe190080 {
-		compatible = "rockchip,rk3568-qos", "syscon";
-		reg = <0x0 0xfe190080 0x0 0x20>;
-	};
-
-	qos_pcie3x2: qos@fe190100 {
-		compatible = "rockchip,rk3568-qos", "syscon";
-		reg = <0x0 0xfe190100 0x0 0x20>;
-	};
-
-	qos_sata0: qos@fe190200 {
-		compatible = "rockchip,rk3568-qos", "syscon";
-		reg = <0x0 0xfe190200 0x0 0x20>;
-	};
-
 	qos_sata1: qos@fe190280 {
 		compatible = "rockchip,rk3568-qos", "syscon";
 		reg = <0x0 0xfe190280 0x0 0x20>;