| Message ID | 20210807104517.24066-1-peng.fan@oss.nxp.com |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: imx8qm: add smmu node | expand |
On Sat, Aug 07, 2021 at 06:45:17PM +0800, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@nxp.com> > > i.MX8QM has an iommu unit: SMMU-V2(mmu-500), add it. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > arch/arm64/boot/dts/freescale/imx8qm.dtsi | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi > index aebbe2b84aa1..b8ffd5be6a3e 100644 > --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi > @@ -165,6 +165,22 @@ iomuxc: pinctrl { > > }; > > + smmu: iommu@51400000 { > + compatible = "arm,mmu-500"; > + reg = <0 0x51400000 0 0x40000>; > + #iommu-cells = <2>; > + #global-interrupts = <1>; > + interrupts = <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, > + <0 32 4>; Use macro to make it more readable. Shawn > + }; > + > /* sorted in register address */ > #include "imx8-ss-img.dtsi" > #include "imx8-ss-dma.dtsi" > -- > 2.30.0 >
On 2021-08-07 11:45, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@nxp.com> > > i.MX8QM has an iommu unit: SMMU-V2(mmu-500), add it. Given CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT, you may want to add this in a disabled state until you've filled in all the "iommus" properties for the client devices. Otherwise, be prepared to hear from people reporting issues bisected to this patch ;) Robin. > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > arch/arm64/boot/dts/freescale/imx8qm.dtsi | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi > index aebbe2b84aa1..b8ffd5be6a3e 100644 > --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi > @@ -165,6 +165,22 @@ iomuxc: pinctrl { > > }; > > + smmu: iommu@51400000 { > + compatible = "arm,mmu-500"; > + reg = <0 0x51400000 0 0x40000>; > + #iommu-cells = <2>; > + #global-interrupts = <1>; > + interrupts = <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, > + <0 32 4>; > + }; > + > /* sorted in register address */ > #include "imx8-ss-img.dtsi" > #include "imx8-ss-dma.dtsi" >
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index aebbe2b84aa1..b8ffd5be6a3e 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -165,6 +165,22 @@ iomuxc: pinctrl { }; + smmu: iommu@51400000 { + compatible = "arm,mmu-500"; + reg = <0 0x51400000 0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>; + }; + /* sorted in register address */ #include "imx8-ss-img.dtsi" #include "imx8-ss-dma.dtsi"