@@ -854,6 +854,25 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
return ret;
}
+static int hw_breakpoint_undef(struct pt_regs *regs, unsigned int instr)
+{
+ int reg = (instr >> 12) & 15;
+
+ /* Fake sticky power-down cleared */
+ regs->uregs[reg] = 0;
+ regs->ARM_pc += 4;
+
+ return 0;
+}
+
+static struct undef_hook hw_breakpoint_hook = {
+ .instr_mask = 0xffff0fff,
+ .instr_val = 0xee110e95,
+ .cpsr_mask = MODE_MASK,
+ .cpsr_val = SVC_MODE,
+ .fn = hw_breakpoint_undef,
+};
+
/*
* One-time initialisation.
*/
@@ -900,6 +919,10 @@ static void reset_ctrl_regs(void *unused)
/*
* Ensure sticky power-down is clear (i.e. debug logic is
* powered up).
+ *
+ * This could raise an undefined instruction exception. If it
+ * does, it is fixed up with an undef hook which constructs
+ * a fake value with the sticky power-down bit cleared.
*/
asm volatile("mrc p14, 0, %0, c1, c5, 4" : "=r" (dbg_power));
if ((dbg_power & 0x1) == 0)
@@ -980,6 +1003,8 @@ static int __init arch_hw_breakpoint_init(void)
core_num_brps = get_num_brps();
core_num_wrps = get_num_wrps();
+ register_undef_hook(&hw_breakpoint_hook);
+
/*
* We need to tread carefully here because DBGSWENABLE may be
* driven low on this core and there isn't an architected way to