[v5,9/9] MAINTAINERS: Add entry for RISC-V PMU drivers

Message ID	20211225054647.1750577-10-atishp@rivosinc.com
State	New
Headers	show Return-Path: <devicetree-owner@kernel.org> From: Atish Patra <atishp@atishpatra.org> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atishp@rivosinc.com>, Albert Ou <aou@eecs.berkeley.edu>, Atish Patra <atishp@atishpatra.org>, Anup Patel <anup@brainfault.org>, Damien Le Moal <damien.lemoal@wdc.com>, devicetree@vger.kernel.org, Jisheng Zhang <jszhang@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>, linux-riscv@lists.infradead.org, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Rob Herring <robh+dt@kernel.org> Subject: [v5 9/9] MAINTAINERS: Add entry for RISC-V PMU drivers Date: Fri, 24 Dec 2021 21:46:47 -0800 Message-Id: <20211225054647.1750577-10-atishp@rivosinc.com> In-Reply-To: <20211225054647.1750577-1-atishp@rivosinc.com> References: <20211225054647.1750577-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Improve RISC-V Perf support using SBI PMU and sscofpmf extension \| expand [v5,0/9] Improve RISC-V Perf support using SBI PMU and sscofpmf extension [v5,1/9] RISC-V: Remove the current perf implementation [v5,2/9] RISC-V: Add CSR encodings for all HPMCOUNTERS [v5,3/9] RISC-V: Add a perf core library for pmu drivers [v5,4/9] RISC-V: Add a simple platform driver for RISC-V legacy perf [v5,5/9] RISC-V: Add RISC-V SBI PMU extension definitions [v5,6/9] RISC-V: Add perf platform driver based on SBI PMU extension [v5,7/9] RISC-V: Add sscofpmf extension support [v5,8/9] Documentation: riscv: Remove the old documentation [v5,9/9] MAINTAINERS: Add entry for RISC-V PMU drivers

Message ID

20211225054647.1750577-10-atishp@rivosinc.com

State

New

Headers

From: Atish Patra <atishp@atishpatra.org>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atishp@rivosinc.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Atish Patra <atishp@atishpatra.org>,
        Anup Patel <anup@brainfault.org>,
        Damien Le Moal <damien.lemoal@wdc.com>,
        devicetree@vger.kernel.org, Jisheng Zhang <jszhang@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
        linux-riscv@lists.infradead.org,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Rob Herring <robh+dt@kernel.org>
Subject: [v5 9/9] MAINTAINERS: Add entry for RISC-V PMU drivers
Date: Fri, 24 Dec 2021 21:46:47 -0800
Message-Id: <20211225054647.1750577-10-atishp@rivosinc.com>
In-Reply-To: <20211225054647.1750577-1-atishp@rivosinc.com>
References: <20211225054647.1750577-1-atishp@rivosinc.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

Series

Improve RISC-V Perf support using SBI PMU and sscofpmf extension | expand

Commit Message

Atish Patra Dec. 25, 2021, 5:46 a.m. UTC

From: Atish Patra <atish.patra@wdc.com>

Add myself and Anup as maintainer for RISC-V PMU drivers.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 MAINTAINERS | 9 +++++++++
 1 file changed, 9 insertions(+)

Comments

Anup Patel Jan. 18, 2022, 5:31 a.m. UTC | #1

On Sat, Dec 25, 2021 at 11:17 AM Atish Patra <atishp@atishpatra.org> wrote:
>
> From: Atish Patra <atish.patra@wdc.com>
>
> Add myself and Anup as maintainer for RISC-V PMU drivers.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
>  MAINTAINERS | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 9af529acb6a6..6232ae05e12c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -16056,6 +16056,15 @@ S:     Maintained
>  F:     drivers/mtd/nand/raw/r852.c
>  F:     drivers/mtd/nand/raw/r852.h
>
> +RISC-V PMU DRIVERS
> +M:     Atish Patra <atishp@atishpatra.org>
> +M:     Anup Patel <anup@brainfault.org>

Please use "R:" instead of "M:" for me.

> +L:     linux-riscv@lists.infradead.org
> +S:     Supported
> +F:     drivers/perf/riscv_pmu.c
> +F:     drivers/perf/riscv_pmu_legacy.c
> +F:     drivers/perf/riscv_pmu_sbi.c
> +
>  RISC-V ARCHITECTURE
>  M:     Paul Walmsley <paul.walmsley@sifive.com>
>  M:     Palmer Dabbelt <palmer@dabbelt.com>
> --
> 2.33.1
>

Regards,
Anup

diff --git a/MAINTAINERS b/MAINTAINERS
index 9af529acb6a6..6232ae05e12c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16056,6 +16056,15 @@  S:	Maintained
 F:	drivers/mtd/nand/raw/r852.c
 F:	drivers/mtd/nand/raw/r852.h
 
+RISC-V PMU DRIVERS
+M:	Atish Patra <atishp@atishpatra.org>
+M:	Anup Patel <anup@brainfault.org>
+L:	linux-riscv@lists.infradead.org
+S:	Supported
+F:	drivers/perf/riscv_pmu.c
+F:	drivers/perf/riscv_pmu_legacy.c
+F:	drivers/perf/riscv_pmu_sbi.c
+
 RISC-V ARCHITECTURE
 M:	Paul Walmsley <paul.walmsley@sifive.com>
 M:	Palmer Dabbelt <palmer@dabbelt.com>

[v5,9/9] MAINTAINERS: Add entry for RISC-V PMU drivers

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Comments

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