| Message ID | 1440942866-23802-5-git-send-email-christoffer.dall@linaro.org |
|---|---|
| State | New |
| Headers | show |
On 30/08/15 14:54, Christoffer Dall wrote: > The GICD_ICFGR allows the bits for the SGIs and PPIs to be read only. > We currently simulate this behavior by writing a hardcoded value to the > register for the SGIs and PPIs on every write of these bits to the > register (ignoring what the guest actually wrote), and by writing the > same value as the reset value to the register. > > This is a bit counter-intuitive, as the register is RO for these bits, > and we can just implement it that way, allowing us to control the value > of the bits purely in the reset code. > > Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> M.
diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c index c5750be..0ba92d3 100644 --- a/virt/kvm/arm/vgic.c +++ b/virt/kvm/arm/vgic.c @@ -655,7 +655,7 @@ bool vgic_handle_cfg_reg(u32 *reg, struct kvm_exit_mmio *mmio, ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); if (mmio->is_write) { if (offset < 8) { - *reg = ~0U; /* Force PPIs/SGIs to 1 */ + /* Ignore writes to read-only SGI and PPI bits */ return false; }
The GICD_ICFGR allows the bits for the SGIs and PPIs to be read only. We currently simulate this behavior by writing a hardcoded value to the register for the SGIs and PPIs on every write of these bits to the register (ignoring what the guest actually wrote), and by writing the same value as the reset value to the register. This is a bit counter-intuitive, as the register is RO for these bits, and we can just implement it that way, allowing us to control the value of the bits purely in the reset code. Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> --- virt/kvm/arm/vgic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)