| Message ID | 20211230195325.328220-3-krzysztof.kozlowski@canonical.com |
|---|---|
| State | Accepted |
| Commit | daeb1c2b50fb98118d6318b5fdbd9ef9bdfaeaf5 |
| Headers | show |
| Series | [RFT,1/3] ARM: dts: exynos: fix UART3 pins configuration in Exynos5250 | expand |
On Thu, 30 Dec 2021 at 21:53, Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> wrote: > > The pin controller device node is expected to have one (optional) > interrupt. Its pin banks capable of external interrupts, should define > interrupts for each pin, unless a muxed interrupt is used. > > Exynos850 defined the second part - interrupt for each pin in wake-up > pin controller - but also added these interrupts in main device node, > which is not correct. > > Fixes: e3493220fd3e ("arm64: dts: exynos: Add initial Exynos850 SoC support") > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> > --- Tested-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Despite some errors brought by this change: samsung-pinctrl 11850000.pinctrl: irq number not available samsung-pinctrl 11c30000.pinctrl: irq number not available the interrupts seem to be functional still. Tested on E850-96 board, by pressing buttons connected to gpa0..gpa1, and checking /proc/interrupts info. I guess it's ok to merge this one as is, and then work further to fix the driver (or dts?) accordingly. Also, I submitted related patch ("arm64: dts: exynos: Add missing gpm6 and gpm7 nodes to Exynos850"), please take a look. > arch/arm64/boot/dts/exynos/exynos850.dtsi | 40 ----------------------- > 1 file changed, 40 deletions(-) > > diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi > index 2abbb972b610..4f0a40de5e67 100644 > --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi > +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi > @@ -344,38 +344,6 @@ cmu_hsi: clock-controller@13400000 { > pinctrl_alive: pinctrl@11850000 { > compatible = "samsung,exynos850-pinctrl"; > reg = <0x11850000 0x1000>; > - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; > > wakeup-interrupt-controller { > compatible = "samsung,exynos7-wakeup-eint"; > @@ -385,14 +353,6 @@ wakeup-interrupt-controller { > pinctrl_cmgp: pinctrl@11c30000 { > compatible = "samsung,exynos850-pinctrl"; > reg = <0x11c30000 0x1000>; > - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; > > wakeup-interrupt-controller { > compatible = "samsung,exynos7-wakeup-eint"; > -- > 2.32.0 >
On Thu, 30 Dec 2021 20:53:25 +0100, Krzysztof Kozlowski wrote: > The pin controller device node is expected to have one (optional) > interrupt. Its pin banks capable of external interrupts, should define > interrupts for each pin, unless a muxed interrupt is used. > > Exynos850 defined the second part - interrupt for each pin in wake-up > pin controller - but also added these interrupts in main device node, > which is not correct. > > [...] Applied, thanks! [3/3] arm64: dts: exynos: drop incorrectly placed wakeup interrupts in Exynos850 commit: daeb1c2b50fb98118d6318b5fdbd9ef9bdfaeaf5 Best regards,
diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index 2abbb972b610..4f0a40de5e67 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -344,38 +344,6 @@ cmu_hsi: clock-controller@13400000 { pinctrl_alive: pinctrl@11850000 { compatible = "samsung,exynos850-pinctrl"; reg = <0x11850000 0x1000>; - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; wakeup-interrupt-controller { compatible = "samsung,exynos7-wakeup-eint"; @@ -385,14 +353,6 @@ wakeup-interrupt-controller { pinctrl_cmgp: pinctrl@11c30000 { compatible = "samsung,exynos850-pinctrl"; reg = <0x11c30000 0x1000>; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; wakeup-interrupt-controller { compatible = "samsung,exynos7-wakeup-eint";
The pin controller device node is expected to have one (optional) interrupt. Its pin banks capable of external interrupts, should define interrupts for each pin, unless a muxed interrupt is used. Exynos850 defined the second part - interrupt for each pin in wake-up pin controller - but also added these interrupts in main device node, which is not correct. Fixes: e3493220fd3e ("arm64: dts: exynos: Add initial Exynos850 SoC support") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> --- arch/arm64/boot/dts/exynos/exynos850.dtsi | 40 ----------------------- 1 file changed, 40 deletions(-)