@@ -23,7 +23,7 @@
active_clk_edges;
chipselect_num = <1>;
- spi-flash@0 {
+ spi_flash: spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@@ -114,6 +114,11 @@
optee {
status = "okay";
};
+ fwu-mdata {
+ compatible = "u-boot,fwu-mdata-sf";
+ fwu-mdata-store = <&spi_flash>;
+ mdata-offsets = <0x500000 0x530000>;
+ };
};
};
@@ -32,4 +32,16 @@ config SYS_CONFIG_NAME
default "synquacer"
endif
+
+config FWU_MULTI_BANK_UPDATE
+ select FWU_MDATA_SF
+ select DM_SPI_FLASH
+ select DM_FWU_MDATA
+
+config FWU_NUM_BANKS
+ default 6
+
+config FWU_NUM_IMAGES_PER_BANK
+ default 1
+
endif
@@ -7,3 +7,4 @@
#
obj-y := developerbox.o
+obj-$(CONFIG_FWU_MULTI_BANK_UPDATE) += fwu_plat.o
new file mode 100644
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021, Linaro Limited
+ */
+
+#include <dfu.h>
+#include <efi_loader.h>
+#include <fwu.h>
+#include <fwu_mdata.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <flash.h>
+
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <u-boot/crc.h>
+
+/* SPI Flash accessors */
+static struct spi_flash *plat_spi_flash;
+
+static int __plat_sf_get_flash(void)
+{
+ struct udevice *new;
+ int ret;
+
+ //TODO: define platform spi-flash somewhere.
+ ret = spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS,
+ CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE,
+ &new);
+ if (ret)
+ return ret;
+
+ plat_spi_flash = dev_get_uclass_priv(new);
+ return 0;
+}
+
+static int plat_sf_get_flash(struct spi_flash **flash)
+{
+ int ret = 0;
+
+ if (!plat_spi_flash)
+ ret = __plat_sf_get_flash();
+
+ *flash = plat_spi_flash;
+
+ return ret;
+}
+
+static int sf_load_data(u32 offs, u32 size, void **data)
+{
+ struct spi_flash *flash;
+ int ret;
+
+ ret = plat_sf_get_flash(&flash);
+ if (ret < 0)
+ return ret;
+
+ *data = memalign(ARCH_DMA_MINALIGN, size);
+ if (!*data)
+ return -ENOMEM;
+
+ ret = spi_flash_read(flash, offs, size, *data);
+ if (ret < 0) {
+ free(*data);
+ *data = NULL;
+ }
+
+ return ret;
+}
+
+/* Platform dependent GUIDs */
+
+/* The GUID for the SNI FIP image type GUID */
+#define FWU_IMAGE_TYPE_DEVBOX_FIP_GUID \
+ EFI_GUID(0x7d6dc310, 0x52ca, 0x43b8, 0xb7, 0xb9, \
+ 0xf9, 0xd6, 0xc5, 0x01, 0xd1, 0x08)
+
+#define PLAT_METADATA_OFFSET 0x510000
+#define PLAT_METADATA_SIZE (sizeof(struct devbox_metadata))
+
+struct __packed devbox_metadata {
+ u32 boot_index;
+ u32 boot_count;
+} *devbox_plat_metadata;
+
+static const efi_guid_t devbox_fip_image_type_guid = FWU_IMAGE_TYPE_DEVBOX_FIP_GUID;
+
+int fwu_plat_get_image_alt_num(efi_guid_t image_type_id, u32 update_bank,
+ int *alt_no)
+{
+ /* DeveloperBox FWU Multi bank only supports FIP image. */
+ if (guidcmp(&image_type_id, &devbox_fip_image_type_guid))
+ return -EOPNOTSUPP;
+
+ /*
+ * DeveloperBox FWU expects Bank:Image = 1:1, and the dfu_alt_info
+ * only has the entries for banks. Thus the alt_no should be equal
+ * to the update_bank.
+ */
+ update_bank %= CONFIG_FWU_NUM_BANKS;
+ *alt_no = update_bank;
+
+ return 0;
+}
+
+efi_status_t fill_image_type_guid_array(const efi_guid_t __always_unused
+ *default_guid,
+ efi_guid_t **part_guid_arr)
+{
+ int i;
+ int alt_num;
+ struct dfu_entity *dfu;
+ efi_status_t ret = EFI_SUCCESS;
+
+ dfu_init_env_entities(NULL, NULL);
+
+ /* TODO: generate DFU and guid array from metadata. */
+ alt_num = 0;
+ list_for_each_entry(dfu, &dfu_list, list) {
+ ++alt_num;
+ }
+
+ if (!alt_num) {
+ log_warning("Probably dfu_alt_info not defined\n");
+ ret = EFI_NOT_READY;
+ goto out;
+ }
+
+ *part_guid_arr = malloc(sizeof(efi_guid_t) * alt_num);
+ if (!*part_guid_arr) {
+ ret = EFI_OUT_OF_RESOURCES;
+ goto out;
+ }
+
+ for (i = 0; i < alt_num; i++)
+ guidcpy((*part_guid_arr + i), &devbox_fip_image_type_guid);
+out:
+ dfu_free_entities();
+
+ return ret;
+}
+
+/* TBD: add a usage counter for wear leveling */
+int fwu_plat_get_update_index(u32 *update_idx)
+{
+ int ret;
+ u32 active_idx;
+
+ ret = fwu_get_active_index(&active_idx);
+
+ if (ret < 0)
+ return -1;
+
+ *update_idx = (active_idx + 1) % CONFIG_FWU_NUM_BANKS;
+
+ return ret;
+}
+
+static int devbox_load_plat_metadata(void)
+{
+ if (devbox_plat_metadata)
+ return 0;
+
+ return sf_load_data(PLAT_METADATA_OFFSET, PLAT_METADATA_SIZE,
+ (void **)&devbox_plat_metadata);
+}
+
+void fwu_plat_get_bootidx(void *boot_idx)
+{
+ u32 *bootidx = boot_idx;
+
+ if (devbox_load_plat_metadata() < 0)
+ *bootidx = 0;
+ else
+ *bootidx = devbox_plat_metadata->boot_index;
+}
@@ -51,8 +51,18 @@
/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
/* #define CONFIG_SYS_PCI_64BIT 1 */
+#ifdef CONFIG_FWU_MULTI_BANK_UPDATE
+#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \
+ "mtd nor1=bank0 raw 600000 400000;" \
+ "bank1 raw a00000 400000;" \
+ "bank2 raw e00000 400000;" \
+ "bank3 raw 1200000 400000;" \
+ "bank4 raw 1600000 400000;" \
+ "bank5 raw 1a00000 400000\0"
+#else
#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \
"mtd nor1=fip.bin raw 600000 400000\0"
+#endif
/* Distro boot settings */
#ifndef CONFIG_SPL_BUILD
The DeveloperBox platform can support the FWU Multi bank update. SCP firmware will switch the boot mode by DSW3-4 and load the Multi bank update supported TF-A BL2 from 0x600000 offset on the SPI flash. Thus it can co-exist with the legacy boot mode (legacy U-Boot or EDK2). Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org> --- .../dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 7 + board/socionext/developerbox/Kconfig | 12 + board/socionext/developerbox/Makefile | 1 board/socionext/developerbox/fwu_plat.c | 178 ++++++++++++++++++++ include/configs/synquacer.h | 10 + 5 files changed, 207 insertions(+), 1 deletion(-) create mode 100644 board/socionext/developerbox/fwu_plat.c