| Message ID | 1645420953-21176-2-git-send-email-quic_rohiagar@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add APCS support for SDX65 | expand |
diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index 01e9d91..688ae8b 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -91,6 +91,7 @@ allOf: compatible: enum: - qcom,sdx55-apcs-gcc + - qcom,sdx65-apcs-gcc then: properties: clocks:
Add devicetree YAML binding for SDX65 APCS GCC block. The APCS block acts as the mailbox controller and also provides a clock output and takes 3 clock sources (pll, aux, ref) as input. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> --- Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml | 1 + 1 file changed, 1 insertion(+)