diff mbox series

[08/10] ASoC: codecs: wsa-macro: setup soundwire clks correctly

Message ID 20220221131037.8809-9-srinivas.kandagatla@linaro.org
State New
Headers show
Series ASoC: codec: add pm runtime support for Qualcomm codecs | expand

Commit Message

Srinivas Kandagatla Feb. 21, 2022, 1:10 p.m. UTC 
For SoundWire Frame sync to be generated correctly we need both MCLK
and MCLKx2 (npl). Without pm runtime enabled these two clocks will remain on,
however after adding pm runtime support its possible that NPl clock could be
turned off even when SoundWire controller is active.

Fix this by enabling mclk and npl clk when SoundWire clks are enabled.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 sound/soc/codecs/lpass-wsa-macro.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/sound/soc/codecs/lpass-wsa-macro.c b/sound/soc/codecs/lpass-wsa-macro.c
index a8d30f3b3fdf..d51d6acac28b 100644
--- a/sound/soc/codecs/lpass-wsa-macro.c
+++ b/sound/soc/codecs/lpass-wsa-macro.c
@@ -2257,6 +2257,7 @@  static int wsa_swrm_clock(struct wsa_macro *wsa, bool enable)
 	struct regmap *regmap = wsa->regmap;
 
 	if (enable) {
+		clk_prepare_enable(wsa->clks[2].clk);
 		wsa_macro_mclk_enable(wsa, true);
 
 		/* reset swr ip */
@@ -2281,6 +2282,7 @@  static int wsa_swrm_clock(struct wsa_macro *wsa, bool enable)
 		regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
 				   CDC_WSA_SWR_CLK_EN_MASK, 0);
 		wsa_macro_mclk_enable(wsa, false);
+		clk_disable_unprepare(wsa->clks[2].clk);
 	}
 
 	return 0;
@@ -2351,7 +2353,7 @@  static int wsa_macro_register_mclk_output(struct wsa_macro *wsa)
 	struct clk_init_data init;
 	int ret;
 
-	parent_clk_name = __clk_get_name(wsa->clks[2].clk);
+	parent_clk_name = __clk_get_name(wsa->clks[3].clk);
 
 	init.name = clk_name;
 	init.ops = &swclk_gate_ops;