| Message ID | 20220313154640.63813-2-michael@walle.cc |
|---|---|
| State | New |
| Headers | show |
| Series | pinctrl: ocelot: add shared reset | expand |
diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml index 40148aef4ecf..cc9e14a214b1 100644 --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml @@ -42,6 +42,14 @@ properties: "#interrupt-cells": const: 2 + resets: + maxItems: 1 + + reset-names: + description: Optional shared switch reset. + items: + - const: switch + required: - compatible - reg
On the LAN966x SoC the GPIO controller will be resetted together with the SGPIO and the switch core. Add a phandle to register the shared reset line. Signed-off-by: Michael Walle <michael@walle.cc> --- .../devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 8 ++++++++ 1 file changed, 8 insertions(+)