diff mbox series

rt-tests: resync has_smi_counter with turbostat code

Message ID CAGCuPdP4jRsupmgWaUF+mRL6R-J3effciUGDw6cybf30-akqAw@mail.gmail.com
State New
Headers show
Series rt-tests: resync has_smi_counter with turbostat code | expand

Commit Message

Bart Wensley April 11, 2022, 3:42 p.m. UTC 
Updating has_smi_counter to match most recent turbostat code, in
order to support recent cpu models (e.g. Ice Lake).

Restructured the code to match the turbostat functions so it will
be easier to keep the code in sync in the future.

Signed-off-by: bartwensley <bwensley@redhat.com>
---
 src/cyclictest/cyclictest.c | 96 +++++++++++++++++++++++++------------
 1 file changed, 65 insertions(+), 31 deletions(-)

        default:
                return 0;
--
2.35.1
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Patch

diff --git a/src/cyclictest/cyclictest.c b/src/cyclictest/cyclictest.c
index c9ed9e0..8673c89 100644
--- a/src/cyclictest/cyclictest.c
+++ b/src/cyclictest/cyclictest.c
@@ -432,39 +432,73 @@  static int has_smi_counter(void)

        model = (((fms >> 16) & 0xf) << 4) + ((fms >> 4) & 0xf);

+       /* Based on intel_model_duplicates */
        switch (model) {
-       case 0x1A:      /* Core i7, Xeon 5500 series - Bloomfield,
Gainstown NHM-EP */
-       case 0x1E:      /* Core i7 and i5 Processor - Clarksfield,
Lynnfield, Jasper Forest */
+       case 0x1A:      /* INTEL_FAM6_NEHALEM_EP */
+       case 0x1E:      /* INTEL_FAM6_NEHALEM */
        case 0x1F:      /* Core i7 and i5 Processor - Nehalem */
-       case 0x25:      /* Westmere Client - Clarkdale, Arrandale */
-       case 0x2C:      /* Westmere EP - Gulftown */
-       case 0x2E:      /* Nehalem-EX Xeon - Beckton */
-       case 0x2F:      /* Westmere-EX Xeon - Eagleton */
-       case 0x2A:      /* SNB */
-       case 0x2D:      /* SNB Xeon */
-       case 0x3A:      /* IVB */
-       case 0x3E:      /* IVB Xeon */
-       case 0x3C:      /* HSW */
-       case 0x3F:      /* HSX */
-       case 0x45:      /* HSW */
-       case 0x46:      /* HSW */
-       case 0x3D:      /* BDW */
-       case 0x47:      /* BDW */
-       case 0x4F:      /* BDX */
-       case 0x56:      /* BDX-DE */
-       case 0x4E:      /* SKL */
-       case 0x5E:      /* SKL */
-       case 0x8E:      /* KBL */
-       case 0x9E:      /* KBL */
-       case 0x55:      /* SKX */
-       case 0x37:      /* BYT */
-       case 0x4D:      /* AVN */
-       case 0x4C:      /* AMT */
-       case 0x57:      /* PHI */
-       case 0x5C:      /* BXT */
-       case 0x5F:      /* DNV */
-       case 0x7A:      /* Gemini Lake */
-       case 0x85:      /* Knights Mill */
+       case 0x25:      /* INTEL_FAM6_WESTMERE */
+       case 0x2C:      /* INTEL_FAM6_WESTMERE_EP */
+               model = 0x1E;      /* INTEL_FAM6_NEHALEM */
+       case 0x2E:      /* INTEL_FAM6_NEHALEM_EX */
+       case 0x2F:      /* INTEL_FAM6_WESTMERE_EX */
+               model = 0x2E;      /* INTEL_FAM6_NEHALEM_EX */
+       case 0x85:      /* INTEL_FAM6_XEON_PHI_KNM */
+               model = 0x57;      /* INTEL_FAM6_XEON_PHI_KNL */
+       case 0x4F:      /* INTEL_FAM6_BROADWELL_X */
+       case 0x56:      /* INTEL_FAM6_BROADWELL_D */
+               model = 0x4F;      /* INTEL_FAM6_BROADWELL_X */
+       case 0x4E:      /* INTEL_FAM6_SKYLAKE_L */
+       case 0x5E:      /* INTEL_FAM6_SKYLAKE */
+       case 0x8E:      /* INTEL_FAM6_KABYLAKE_L */
+       case 0x9E:      /* INTEL_FAM6_KABYLAKE */
+       case 0xA6:      /* INTEL_FAM6_COMETLAKE_L */
+       case 0xA5:      /* INTEL_FAM6_COMETLAKE */
+               model = 0x4E;      /* INTEL_FAM6_SKYLAKE_L */
+       case 0x7E:      /* INTEL_FAM6_ICELAKE_L */
+       case 0x9D:      /* INTEL_FAM6_ICELAKE_NNPI */
+       case 0x8C:      /* INTEL_FAM6_TIGERLAKE_L */
+       case 0x8D:      /* INTEL_FAM6_TIGERLAKE */
+       case 0xA7:      /* INTEL_FAM6_ROCKETLAKE */
+       case 0x8A:      /* INTEL_FAM6_LAKEFIELD */
+       case 0x97:      /* INTEL_FAM6_ALDERLAKE */
+       case 0x9A:      /* INTEL_FAM6_ALDERLAKE_L */
+               model = 0x66;      /* INTEL_FAM6_CANNONLAKE_L */
+       case 0x9C:      /* INTEL_FAM6_ATOM_TREMONT_L */
+               model = 0x96;      /* INTEL_FAM6_ATOM_TREMONT */
+       case 0x6C:      /* INTEL_FAM6_ICELAKE_D */
+       case 0x8F:      /* INTEL_FAM6_SAPPHIRERAPIDS_X */
+               model = 0x6A;      /* INTEL_FAM6_ICELAKE_X */
+       }
+
+       /* Based on probe_nhm_msrs */
+       switch (model) {
+       case 0x1E:      /* INTEL_FAM6_NEHALEM */
+       case 0x2E:      /* INTEL_FAM6_NEHALEM_EX */
+       case 0x2A:      /* INTEL_FAM6_SANDYBRIDGE */
+       case 0x2D:      /* INTEL_FAM6_SANDYBRIDGE_X */
+       case 0x3A:      /* INTEL_FAM6_IVYBRIDGE */
+       case 0x3E:      /* INTEL_FAM6_IVYBRIDGE_X */
+       case 0x3C:      /* INTEL_FAM6_HASWELL */
+       case 0x46:      /* INTEL_FAM6_HASWELL_G */
+       case 0x3F:      /* INTEL_FAM6_HASWELL_X */
+       case 0x45:      /* INTEL_FAM6_HASWELL_L */
+       case 0x3D:      /* INTEL_FAM6_BROADWELL */
+       case 0x47:      /* INTEL_FAM6_BROADWELL_G */
+       case 0x4F:      /* INTEL_FAM6_BROADWELL_X */
+       case 0x4E:      /* INTEL_FAM6_SKYLAKE_L */
+       case 0x66:      /* INTEL_FAM6_CANNONLAKE_L */
+       case 0x55:      /* INTEL_FAM6_SKYLAKE_X */
+       case 0x6A:      /* INTEL_FAM6_ICELAKE_X */
+       case 0x37:      /* INTEL_FAM6_ATOM_SILVERMONT */
+       case 0x4D:      /* INTEL_FAM6_ATOM_SILVERMONT_D */
+       case 0x4C:      /* INTEL_FAM6_ATOM_AIRMONT */
+       case 0x57:      /* INTEL_FAM6_XEON_PHI_KNL */
+       case 0x5C:      /* INTEL_FAM6_ATOM_GOLDMONT */
+       case 0x7A:      /* INTEL_FAM6_ATOM_GOLDMONT_PLUS */
+       case 0x5F:      /* INTEL_FAM6_ATOM_GOLDMONT_D */
+       case 0x96:      /* INTEL_FAM6_ATOM_TREMONT */
+       case 0x86:      /* INTEL_FAM6_ATOM_TREMONT_D */
                break;