| Message ID | 20220423133939.2123449-5-dmitry.baryshkov@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: qcom: Fix higher MSI vectors handling | expand |
On 23/04/2022 19:37, Krzysztof Kozlowski wrote: > On 23/04/2022 15:39, Dmitry Baryshkov wrote: >> On Qualcomm platforms each group of 32 MSI vectors is routed to the >> separate GIC interrupt. Document mapping of additional interrupts. > > Is it on every Qualcomm platform? How many per each variant? IOW, this > should have a per-compatible constraints, if possible. After discussions on IRC, that finding such per-variant constraints is tricky: Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 04fda2a4bb60..71b3be5570dd 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -49,11 +49,21 @@ properties: - atu # ATU address space (optional) interrupts: - maxItems: 1 + minItems: 1 + maxItems: 8 interrupt-names: + minItems: 1 + maxItems: 8 items: - - const: "msi" + - const: msi + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + - const: msi8 # Common definitions for clocks, clock-names and reset. # Platform constraints are described later.
On Qualcomm platforms each group of 32 MSI vectors is routed to the separate GIC interrupt. Document mapping of additional interrupts. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- .../devicetree/bindings/pci/qcom,pcie.yaml | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-)