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[3/5] bus: mhi: host: Use {READ/WITE}_ONCE macros for db_mode and db_val

Message ID 20220502104144.91806-4-manivannan.sadhasivam@linaro.org
State New
Headers show
Series [1/5] bus: mhi: host: Rename process_db callback to ring_db | expand

Commit Message

Manivannan Sadhasivam May 2, 2022, 10:41 a.m. UTC 
In order to prevent the compiler from optimizing these fields that could
be used parallely, let's use the {READ/WRITE}_ONCE macros for reading and
updating. Since these fields are defined as bool, let's use the true/false
instead of 0/1.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 drivers/bus/mhi/host/init.c |  4 ++--
 drivers/bus/mhi/host/main.c | 14 +++++++++-----
 2 files changed, 11 insertions(+), 7 deletions(-)
diff mbox series

Patch

diff --git a/drivers/bus/mhi/host/init.c b/drivers/bus/mhi/host/init.c
index e095d2999c06..906bdf584860 100644
--- a/drivers/bus/mhi/host/init.c
+++ b/drivers/bus/mhi/host/init.c
@@ -325,7 +325,7 @@  int mhi_init_dev_ctxt(struct mhi_controller *mhi_cntrl)
 
 		er_ctxt->ertype = cpu_to_le32(MHI_ER_TYPE_VALID);
 		er_ctxt->msivec = cpu_to_le32(mhi_event->irq);
-		mhi_event->db_cfg.db_mode = true;
+		WRITE_ONCE(mhi_event->db_cfg.db_mode, true);
 
 		ring->el_size = sizeof(struct mhi_ring_element);
 		ring->len = ring->el_size * ring->elements;
@@ -615,7 +615,7 @@  int mhi_init_chan_ctxt(struct mhi_controller *mhi_cntrl,
 
 	tre_ring->rp = tre_ring->wp = tre_ring->base;
 	buf_ring->rp = buf_ring->wp = buf_ring->base;
-	mhi_chan->db_cfg.db_mode = 1;
+	WRITE_ONCE(mhi_chan->db_cfg.db_mode, true);
 
 	/* Update to all cores */
 	smp_wmb();
diff --git a/drivers/bus/mhi/host/main.c b/drivers/bus/mhi/host/main.c
index 28b41621e004..bb3b20207c4e 100644
--- a/drivers/bus/mhi/host/main.c
+++ b/drivers/bus/mhi/host/main.c
@@ -92,10 +92,14 @@  void mhi_ring_db_brstmode(struct mhi_controller *mhi_cntrl,
 		     void __iomem *db_addr,
 		     dma_addr_t db_val)
 {
-	if (db_cfg->db_mode) {
-		db_cfg->db_val = db_val;
+	if (READ_ONCE(db_cfg->db_mode)) {
+		/*
+		 * There is no barrier required here, since both compiler and
+		 * CPU will honor the load/store control dependency.
+		 */
+		WRITE_ONCE(db_cfg->db_val, db_val);
 		mhi_write_db(mhi_cntrl, db_addr, db_val);
-		db_cfg->db_mode = 0;
+		WRITE_ONCE(db_cfg->db_mode, false);
 	}
 }
 
@@ -104,7 +108,7 @@  void mhi_ring_db_no_brstmode(struct mhi_controller *mhi_cntrl,
 			     void __iomem *db_addr,
 			     dma_addr_t db_val)
 {
-	db_cfg->db_val = db_val;
+	WRITE_ONCE(db_cfg->db_val, db_val);
 	mhi_write_db(mhi_cntrl, db_addr, db_val);
 }
 
@@ -665,7 +669,7 @@  static int parse_xfer_event(struct mhi_controller *mhi_cntrl,
 	{
 		unsigned long pm_lock_flags;
 
-		mhi_chan->db_cfg.db_mode = 1;
+		WRITE_ONCE(mhi_chan->db_cfg.db_mode, true);
 		read_lock_irqsave(&mhi_cntrl->pm_lock, pm_lock_flags);
 		if (tre_ring->wp != tre_ring->rp &&
 		    MHI_DB_ACCESS_VALID(mhi_cntrl)) {