diff mbox series

[4/4] spi: synquacer: simplify tx completion checking

Message ID 20220517084139.6986-5-masahisa.kojima@linaro.org
State Accepted
Commit f81aaa0b33bec4292838e75d14a0653775aea45d
Headers show
Series spi-synquacer fixes and improvement | expand

Commit Message

Masahisa Kojima May 17, 2022, 8:41 a.m. UTC 
There is a TX-FIFO and Shift Register empty(TFES) status
bit in spi controller. This commit checks the TFES bit
to wait the TX transfer completes.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com>
---
 drivers/spi/spi-synquacer.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

Comments

Jassi Brar May 18, 2022, 3:43 a.m. UTC | #1 
On Tue, 17 May 2022 at 03:41, Masahisa Kojima
<masahisa.kojima@linaro.org> wrote:
>
> There is a TX-FIFO and Shift Register empty(TFES) status
> bit in spi controller. This commit checks the TFES bit
> to wait the TX transfer completes.
>
> Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com>
> ---
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
Tom Rini June 10, 2022, 9:40 p.m. UTC | #2 
On Tue, May 17, 2022 at 05:41:39PM +0900, Masahisa Kojima wrote:

> There is a TX-FIFO and Shift Register empty(TFES) status
> bit in spi controller. This commit checks the TFES bit
> to wait the TX transfer completes.
> 
> Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com>
> Acked-by: Jassi Brar <jaswinder.singh@linaro.org>

Applied to u-boot/next, thanks!
diff mbox series

Patch

diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c
index 5e1b3aedc7..0cae3dfc77 100644
--- a/drivers/spi/spi-synquacer.c
+++ b/drivers/spi/spi-synquacer.c
@@ -45,6 +45,7 @@ 
 #define RXF		0x20
 #define RXE		0x24
 #define RXC		0x28
+#define TFES		1
 #define TFLETE		4
 #define TSSRS		6
 #define RFMTE		5
@@ -345,13 +346,10 @@  static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen,
 		if (priv->tx_words) {
 			write_fifo(priv);
 		} else {
-			u32 len;
-
-			do { /* wait for shifter to empty out */
+			/* wait for shifter to empty out */
+			while (!(readl(priv->base + TXF) & BIT(TFES)))
 				cpu_relax();
-				len = readl(priv->base + DMSTATUS);
-				len = (len >> TX_DATA_SHIFT) & TX_DATA_MASK;
-			} while (tx_buf && len);
+
 			busy &= ~BIT(TXBIT);
 		}
 	}