| Message ID | 1451505909-3820-1-git-send-email-linus.walleij@linaro.org |
|---|---|
| State | Accepted |
| Commit | ef2a27059226327228238a55208d8c11b80013c9 |
| Headers | show |
diff --git a/arch/arm/boot/dts/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm-realview-pb11mp.dts index 28bd5aea285f..3d9b1b0f4ffc 100644 --- a/arch/arm/boot/dts/arm-realview-pb11mp.dts +++ b/arch/arm/boot/dts/arm-realview-pb11mp.dts @@ -99,6 +99,19 @@ <0 31 IRQ_TYPE_LEVEL_HIGH>; cache-unified; cache-level = <2>; + /* + * Override default cache size, sets and + * associativity as these may be erroneously set + * up by boot loader(s), probably for safety + * since th outer sync operation can cause the + * cache to hang unless disabled. + */ + cache-size = <1048576>; // 1MB + cache-sets = <4096>; + cache-line-size = <32>; + arm,shared-override; + arm,parity-enable; + arm,outer-sync-disable; }; scu@1f000000 {
The L2 cache comes up in a "safe mode" on the PB11MPCore, as it has several issues. This sets it up properly with the right size and associativity, also requiring the outer sync to be disabled for the machine to boot properly. Cc: Russell King <linux@arm.linux.org.uk> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> --- ARM SoC folks: Russell has merged the outer cache sync disable patch so it would be nice if you'd merge this directly on top of the branch holding the PB11MPCore device tree, so that the cache is feature complete for v4.5. --- arch/arm/boot/dts/arm-realview-pb11mp.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.4.3 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel