| Message ID | 20220722125730.3428017-9-peng.fan@oss.nxp.com |
|---|---|
| State | New |
| Headers | show |
| Series | imx: add i.MX8MP hdmi blk ctrl hdcp/hrv and vpu blk ctrl | expand |
On Fri, Jul 22, 2022 at 08:57:30PM +0800, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@nxp.com> > > Add i.MX8MP VPU blk ctrl node > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > index 34af983b0210..493fc3ceec1f 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > @@ -1185,6 +1185,24 @@ gic: interrupt-controller@38800000 { > interrupt-parent = <&gic>; > }; > > + vpumix_blk_ctrl: blk-ctrl@38330000 { Please add it in order of unit-address. Shawn > + compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; > + reg = <0x38330000 0x100>; > + #power-domain-cells = <1>; > + power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, > + <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>; > + power-domain-names = "bus", "g1", "g2", "vc8000e"; > + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, > + <&clk IMX8MP_CLK_VPU_G2_ROOT>, > + <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; > + clock-names = "g1", "g2", "vc8000e"; > + interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, > + <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, > + <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>; > + interconnect-names = "g1", "g2", "vc8000e"; > + }; > + > + > edacmc: memory-controller@3d400000 { > compatible = "snps,ddrc-3.80a"; > reg = <0x3d400000 0x400000>; > -- > 2.25.1 >
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 34af983b0210..493fc3ceec1f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1185,6 +1185,24 @@ gic: interrupt-controller@38800000 { interrupt-parent = <&gic>; }; + vpumix_blk_ctrl: blk-ctrl@38330000 { + compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; + reg = <0x38330000 0x100>; + #power-domain-cells = <1>; + power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, + <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>; + power-domain-names = "bus", "g1", "g2", "vc8000e"; + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, + <&clk IMX8MP_CLK_VPU_G2_ROOT>, + <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; + clock-names = "g1", "g2", "vc8000e"; + interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, + <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, + <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>; + interconnect-names = "g1", "g2", "vc8000e"; + }; + + edacmc: memory-controller@3d400000 { compatible = "snps,ddrc-3.80a"; reg = <0x3d400000 0x400000>;