[net-next,11/12] net: ethernet: mtk_eth_wed: add axi bus support

Message ID	09011397a0f4d6ba017abc0dc396e8be990e72aa.1662661555.git.lorenzo@kernel.org
State	New
Headers	show Return-Path: <devicetree-owner@kernel.org> From: Lorenzo Bianconi <lorenzo@kernel.org> To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, matthias.bgg@gmail.com, linux-mediatek@lists.infradead.org, lorenzo.bianconi@redhat.com, Bo.Jiao@mediatek.com, sujuan.chen@mediatek.com, ryder.Lee@mediatek.com, evelyn.tsai@mediatek.com, devicetree@vger.kernel.org, robh@kernel.org Subject: [PATCH net-next 11/12] net: ethernet: mtk_eth_wed: add axi bus support Date: Thu, 8 Sep 2022 21:33:45 +0200 Message-Id: <09011397a0f4d6ba017abc0dc396e8be990e72aa.1662661555.git.lorenzo@kernel.org> In-Reply-To: <cover.1662661555.git.lorenzo@kernel.org> References: <cover.1662661555.git.lorenzo@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	[net-next,01/12] arm64: dts: mediatek: mt7986: add support for Wireless Ethernet Dispatch \| expand [net-next,01/12] arm64: dts: mediatek: mt7986: add support for Wireless Ethernet Dispatch [net-next,03/12] net: ethernet: mtk_eth_soc: move gdma_to_ppe and ppe_base definitions in mtk reg... [net-next,05/12] net: ethernet: mtk_eth_soc: add the capability to run multiple ppe [net-next,07/12] net: ethernet: mtk_eth_soc: add foe_entry_size to mtk_eth_soc [net-next,09/12] net: ethernet: mtk_eth_wed: add mtk_wed_configure_irq and mtk_wed_dma_{enable/di... [net-next,11/12] net: ethernet: mtk_eth_wed: add axi bus support

diff --git a/drivers/net/ethernet/mediatek/mtk_wed.c b/drivers/net/ethernet/mediatek/mtk_wed.c index 3ec891f05fa7..48c638c49355 100644 --- a/drivers/net/ethernet/mediatek/mtk_wed.c +++ b/drivers/net/ethernet/mediatek/mtk_wed.c @@ -85,11 +85,31 @@ static struct mtk_wed_hw * mtk_wed_assign(struct mtk_wed_device *dev) { struct mtk_wed_hw *hw; + int i; + + if (dev->wlan.bus_type == MTK_WED_BUS_PCIE) { + hw = hw_list[pci_domain_nr(dev->wlan.pci_dev->bus)]; + if (!hw) + return NULL; + + if (!hw->wed_dev) + goto out; + + if (hw->version == 1) + return NULL; + + /* MT7986 WED devices do not have any pcie slot restrictions */ + } + /* MT7986 PCIE or AXI */ + for (i = 0; i < ARRAY_SIZE(hw_list); i++) { + hw = hw_list[i]; + if (hw && !hw->wed_dev) + goto out; + } - hw = hw_list[pci_domain_nr(dev->wlan.pci_dev->bus)]; - if (!hw || hw->wed_dev) - return NULL; + return NULL; +out: hw->wed_dev = dev; return hw; } @@ -321,7 +341,6 @@ mtk_wed_stop(struct mtk_wed_device *dev) static void mtk_wed_detach(struct mtk_wed_device *dev) { - struct device_node *wlan_node = dev->wlan.pci_dev->dev.of_node; struct mtk_wed_hw *hw = dev->hw; mutex_lock(&hw_lock); @@ -336,9 +355,14 @@ mtk_wed_detach(struct mtk_wed_device *dev) mtk_wed_free_buffer(dev); mtk_wed_free_tx_rings(dev); - if (of_dma_is_coherent(wlan_node) && hw->hifsys) - regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP, - BIT(hw->index), BIT(hw->index)); + if (dev->wlan.bus_type == MTK_WED_BUS_PCIE) { + struct device_node *wlan_node; + + wlan_node = dev->wlan.pci_dev->dev.of_node; + if (of_dma_is_coherent(wlan_node) && hw->hifsys) + regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP, + BIT(hw->index), BIT(hw->index)); + } if (!hw_list[!hw->index]->wed_dev && hw->eth->dma_dev != hw->eth->dev) @@ -355,42 +379,55 @@ mtk_wed_detach(struct mtk_wed_device *dev) static void mtk_wed_bus_init(struct mtk_wed_device *dev) { - struct device_node *node; - void __iomem *base_addr; - u32 val; - - node = of_parse_phandle(dev->hw->node, "mediatek,wed_pcie", 0); - if (!node) - return; + switch (dev->wlan.bus_type) { + case MTK_WED_BUS_PCIE: { + struct device_node *node; + void __iomem *base_addr; + u32 val; + + node = of_parse_phandle(dev->hw->node, "mediatek,wed_pcie", 0); + if (!node) + break; - base_addr = of_iomap(node, 0); - val = BIT(0) | readl(base_addr); - writel(val, base_addr); + base_addr = of_iomap(node, 0); + val = BIT(0) | readl(base_addr); + writel(val, base_addr); - wed_w32(dev, MTK_WED_PCIE_INT_CTRL, - FIELD_PREP(MTK_WED_PCIE_INT_CTRL_POLL_EN, 2)); + wed_w32(dev, MTK_WED_PCIE_INT_CTRL, + FIELD_PREP(MTK_WED_PCIE_INT_CTRL_POLL_EN, 2)); - /* pcie interrupt control: pola/source selection */ - wed_set(dev, MTK_WED_PCIE_INT_CTRL, - MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA | - FIELD_PREP(MTK_WED_PCIE_INT_CTRL_SRC_SEL, 1)); - wed_r32(dev, MTK_WED_PCIE_INT_CTRL); + /* pcie interrupt control: pola/source selection */ + wed_set(dev, MTK_WED_PCIE_INT_CTRL, + MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA | + FIELD_PREP(MTK_WED_PCIE_INT_CTRL_SRC_SEL, 1)); + wed_r32(dev, MTK_WED_PCIE_INT_CTRL); - val = wed_r32(dev, MTK_WED_PCIE_CFG_INTM); - val = wed_r32(dev, MTK_WED_PCIE_CFG_BASE); - wed_w32(dev, MTK_WED_PCIE_CFG_INTM, PCIE_BASE_ADDR0 | 0x180); - wed_w32(dev, MTK_WED_PCIE_CFG_BASE, PCIE_BASE_ADDR0 | 0x184); + val = wed_r32(dev, MTK_WED_PCIE_CFG_INTM); + val = wed_r32(dev, MTK_WED_PCIE_CFG_BASE); + wed_w32(dev, MTK_WED_PCIE_CFG_INTM, PCIE_BASE_ADDR0 | 0x180); + wed_w32(dev, MTK_WED_PCIE_CFG_BASE, PCIE_BASE_ADDR0 | 0x184); - val = wed_r32(dev, MTK_WED_PCIE_CFG_INTM); - val = wed_r32(dev, MTK_WED_PCIE_CFG_BASE); + val = wed_r32(dev, MTK_WED_PCIE_CFG_INTM); + val = wed_r32(dev, MTK_WED_PCIE_CFG_BASE); - /* pcie interrupt status trigger register */ - wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(24)); - wed_r32(dev, MTK_WED_PCIE_INT_TRIGGER); + /* pcie interrupt status trigger register */ + wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(24)); + wed_r32(dev, MTK_WED_PCIE_INT_TRIGGER); - /* pola setting */ - val = wed_r32(dev, MTK_WED_PCIE_INT_CTRL); - wed_set(dev, MTK_WED_PCIE_INT_CTRL, MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA); + /* pola setting */ + val = wed_r32(dev, MTK_WED_PCIE_INT_CTRL); + wed_set(dev, MTK_WED_PCIE_INT_CTRL, + MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA); + break; + } + case MTK_WED_BUS_AXI: + wed_set(dev, MTK_WED_WPDMA_INT_CTRL, + MTK_WED_WPDMA_INT_CTRL_SIG_SRC | + FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_SRC_SEL, 0)); + break; + default: + break; + } } static void @@ -800,7 +837,8 @@ mtk_wed_attach(struct mtk_wed_device *dev) RCU_LOCKDEP_WARN(!rcu_read_lock_held(), "mtk_wed_attach without holding the RCU read lock"); - if (pci_domain_nr(dev->wlan.pci_dev->bus) > 1 || + if ((dev->wlan.bus_type == MTK_WED_BUS_PCIE && + pci_domain_nr(dev->wlan.pci_dev->bus) > 1) || !try_module_get(THIS_MODULE)) ret = -ENODEV; diff --git a/drivers/net/ethernet/mediatek/mtk_wed_regs.h b/drivers/net/ethernet/mediatek/mtk_wed_regs.h index ecd925fbd451..1e2aafc10f4c 100644 --- a/drivers/net/ethernet/mediatek/mtk_wed_regs.h +++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h @@ -194,6 +194,8 @@ struct mtk_wdma_desc { #define MTK_WED_WPDMA_INT_CTRL 0x520 #define MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV BIT(21) +#define MTK_WED_WPDMA_INT_CTRL_SIG_SRC BIT(22) +#define MTK_WED_WPDMA_INT_CTRL_SRC_SEL GENMASK(17, 16) #define MTK_WED_WPDMA_INT_MASK 0x524 diff --git a/include/linux/soc/mediatek/mtk_wed.h b/include/linux/soc/mediatek/mtk_wed.h index 592221a7149b..f2ae5bd140a1 100644 --- a/include/linux/soc/mediatek/mtk_wed.h +++ b/include/linux/soc/mediatek/mtk_wed.h @@ -11,6 +11,11 @@ struct mtk_wed_hw; struct mtk_wdma_desc; +enum mtk_wed_bus_tye { + MTK_WED_BUS_PCIE, + MTK_WED_BUS_AXI, +}; + struct mtk_wed_ring { struct mtk_wdma_desc *desc; dma_addr_t desc_phys; @@ -45,6 +50,8 @@ struct mtk_wed_device { struct { struct pci_dev *pci_dev; + enum mtk_wed_bus_tye bus_type; + u32 wpdma_phys; u32 wpdma_int; u32 wpdma_mask;

[net-next,11/12] net: ethernet: mtk_eth_wed: add axi bus support

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