diff mbox series

[2/2] board: developerbox: move mem_map setup later

Message ID 20220912170529.719048-1-jassisinghbrar@gmail.com
State New
Headers show
Series [1/2] board: developerbox: use identity mapping for >4GB | expand

Commit Message

Jassi Brar Sept. 12, 2022, 5:05 p.m. UTC 
From: Jassi Brar <jaswinder.singh@linaro.org>

dram_init() can't modify global/static variables, so
move the mem_map setup later when bss is available.

Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
---
 board/socionext/developerbox/developerbox.c | 57 ++++++++++++---------
 1 file changed, 34 insertions(+), 23 deletions(-)

Comments

Tom Rini Oct. 7, 2022, 3:47 p.m. UTC | #1 
On Mon, Sep 12, 2022 at 12:05:29PM -0500, jassisinghbrar@gmail.com wrote:

> From: Jassi Brar <jaswinder.singh@linaro.org>
> 
> dram_init() can't modify global/static variables, so
> move the mem_map setup later when bss is available.
> 
> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>

Applied to u-boot/master, thanks!
diff mbox series

Patch

diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c
index b680f77d80..412c811c12 100644
--- a/board/socionext/developerbox/developerbox.c
+++ b/board/socionext/developerbox/developerbox.c
@@ -56,8 +56,6 @@  struct draminfo {
 	struct draminfo_entry	entry[3];
 };
 
-struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
-
 DECLARE_GLOBAL_DATA_PTR;
 
 #define LOAD_OFFSET 0x100
@@ -104,21 +102,44 @@  int ft_board_setup(void *blob, struct bd_info *bd)
 
 int dram_init(void)
 {
+	struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
+	struct draminfo_entry *ent = synquacer_draminfo->entry;
+
+	gd->ram_size = ent[0].size;
+	gd->ram_base = ent[0].base;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
+	struct draminfo_entry *ent = synquacer_draminfo->entry;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) {
+		if (i < synquacer_draminfo->nr_regions) {
+			debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base);
+			gd->bd->bi_dram[i].start = ent[i].base;
+			gd->bd->bi_dram[i].size = ent[i].size;
+		}
+	}
+
+	return 0;
+}
+
+void build_mem_map(void)
+{
+	struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
 	struct draminfo_entry *ent = synquacer_draminfo->entry;
 	struct mm_region *mr;
 	int i, ri;
 
 	if (synquacer_draminfo->nr_regions < 1) {
 		log_err("Failed to get correct DRAM information\n");
-		return -1;
+		return;
 	}
 
-	/*
-	 * U-Boot RAM size must be under the first DRAM region so that it doesn't
-	 * access secure memory which is at the end of the first DRAM region.
-	 */
-	gd->ram_size = ent[0].size;
-
 	/* Update memory region maps */
 	for (i = 0; i < synquacer_draminfo->nr_regions; i++) {
 		if (i >= MAX_DDR_REGIONS)
@@ -134,24 +155,14 @@  int dram_init(void)
 		mr = &mem_map[DDR_REGION_INDEX(0)];
 		mem_map[ri].attrs = mr->attrs;
 	}
-
-	return 0;
 }
 
-int dram_init_banksize(void)
+void enable_caches(void)
 {
-	struct draminfo_entry *ent = synquacer_draminfo->entry;
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) {
-		if (i < synquacer_draminfo->nr_regions) {
-			debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base);
-			gd->bd->bi_dram[i].start = ent[i].base;
-			gd->bd->bi_dram[i].size = ent[i].size;
-		}
-	}
+	build_mem_map();
 
-	return 0;
+	icache_enable();
+	dcache_enable();
 }
 
 int print_cpuinfo(void)