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[5/7] dt-bindings: iommu: qcom,iommu: Document QSMMU v2 compatibles

Message ID 20221111135525.204134-6-angelogioacchino.delregno@collabora.com
State Superseded
Headers show
Series Add support for Qualcomm's legacy IOMMU v2 | expand

Commit Message

AngeloGioacchino Del Regno Nov. 11, 2022, 1:55 p.m. UTC 
Add compatible strings for "qcom,msm-iommu-v2" for the inner node,
"qcom,msm-iommu-v2-ns" and "qcom,msm-iommu-v2-sec" for the context
bank nodes to support Qualcomm's secure fw "SMMU v2" implementation.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 Documentation/devicetree/bindings/iommu/qcom,iommu.txt | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)
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Patch

diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt
index 7d4e0a18b08e..b762772f80e7 100644
--- a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt
+++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt
@@ -11,7 +11,10 @@  to non-secure vs secure interrupt line.
 
                         "qcom,msm8916-iommu"
 
-                     Followed by "qcom,msm-iommu-v1".
+                     Followed by one of:
+
+                        - "qcom,msm-iommu-v1"
+                        - "qcom,msm-iommu-v2"
 
 - clock-names      : Should be a pair of "iface" (required for IOMMUs
                      register group access) and "bus" (required for
@@ -36,6 +39,8 @@  to non-secure vs secure interrupt line.
   - compatible     : Should be one of:
         - "qcom,msm-iommu-v1-ns"  : non-secure context bank
         - "qcom,msm-iommu-v1-sec" : secure context bank
+        - "qcom,msm-iommu-v2-ns"  : non-secure QSMMUv2/QSMMU500 context bank
+        - "qcom,msm-iommu-v2-sec" : secure QSMMUv2/QSMMU500 context bank
   - reg            : Base address and size of context bank within the iommu
   - interrupts     : The context fault irq.