| Message ID | 20221201084229.3464449-4-wenst@chromium.org |
|---|---|
| State | Accepted |
| Commit | 0f1c806b65d136a5fe0b88adad5ff1cb451fc401 |
| Headers | show |
| Series | arm64: dts: mediatek: Fix systimer clock description | expand |
Il 01/12/22 09:42, Chen-Yu Tsai ha scritto: > The systimer block derives its 13 MHz clock by dividing the main 26 MHz > oscillator clock by 2 internally, not through the TOPCKGEN clock > controller. > > On the MT8195 this divider is set either by power-on-reset or by the > bootloader. The bootloader may then make the divider unconfigurable to, > but can be read out by, the operating system. > > Making the systimer block take the 26 MHz clock directly requires > changing the implementations. As an ABI compatible fix, change the > input clock of the systimer block a fixed factor divide-by-2 clock > that takes the 26 MHz oscillator as its input. > > Fixes: 37f2582883be ("arm64: dts: Add mediatek SoC mt8195 and evaluation board") > Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 5d31536f4c48..60e15833956e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -248,6 +248,15 @@ sound: mt8195-sound { status = "disabled"; }; + clk13m: fixed-factor-clock-13m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk26m>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "clk13m"; + }; + clk26m: oscillator-26m { compatible = "fixed-clock"; #clock-cells = <0>; @@ -705,7 +714,7 @@ systimer: timer@10017000 { "mediatek,mt6765-timer"; reg = <0 0x10017000 0 0x1000>; interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&topckgen CLK_TOP_CLK26M_D2>; + clocks = <&clk13m>; }; pwrap: pwrap@10024000 {
The systimer block derives its 13 MHz clock by dividing the main 26 MHz oscillator clock by 2 internally, not through the TOPCKGEN clock controller. On the MT8195 this divider is set either by power-on-reset or by the bootloader. The bootloader may then make the divider unconfigurable to, but can be read out by, the operating system. Making the systimer block take the 26 MHz clock directly requires changing the implementations. As an ABI compatible fix, change the input clock of the systimer block a fixed factor divide-by-2 clock that takes the 26 MHz oscillator as its input. Fixes: 37f2582883be ("arm64: dts: Add mediatek SoC mt8195 and evaluation board") Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)