| Message ID | 20221207062913.3154262-1-bhupesh.sharma@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: qcom: sm8150: Fix iommu sid values for PCIe nodes | expand |
Hi Bhupesh,
I love your patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on linus/master v6.1-rc8 next-20221207]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Bhupesh-Sharma/arm64-dts-qcom-sm8150-Fix-iommu-sid-values-for-PCIe-nodes/20221207-143044
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20221207062913.3154262-1-bhupesh.sharma%40linaro.org
patch subject: [PATCH] arm64: dts: qcom: sm8150: Fix iommu sid values for PCIe nodes
config: arm64-randconfig-r026-20221207
compiler: aarch64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/8e9bc365874888e1e06f348add387ae3c3415ae6
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Bhupesh-Sharma/arm64-dts-qcom-sm8150-Fix-iommu-sid-values-for-PCIe-nodes/20221207-143044
git checkout 8e9bc365874888e1e06f348add387ae3c3415ae6
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> Error: arch/arm64/boot/dts/qcom/sm8150.dtsi:1816.9-10 syntax error
FATAL ERROR: Unable to parse input tree
On 07/12/2022 07:29, Bhupesh Sharma wrote: > Fix the iommu sid values for the PCIe nodes present on > Qualcomm SM8150 SoC dtsi (in sync the with downstream code). > > Fixes: a1c86c680533 ("arm64: dts: qcom: sm8150: Add PCIe nodes") > Cc: Bjorn Andersson <andersson@kernel.org> > Cc: Rob Herring <robh+dt@kernel.org> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8150.dtsi | 32 ++++++++++++++++++++++++++-- > 1 file changed, 30 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi > index d1b64280ab0b..e88d1617a1ab 100644 > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi > @@ -1810,9 +1810,23 @@ pcie0: pci@1c00000 { > "slave_q2a", > "tbu"; > > - iommus = <&apps_smmu 0x1d80 0x7f>; > + iommus = <&apps_smmu 0x1d80 0xf>; > iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, > <0x100 &apps_smmu 0x1d81 0x1>; Should be a "," here. > + <0x200 &apps_smmu 0x1d82 0x1>, > + <0x300 &apps_smmu 0x1d83 0x1>, > + <0x400 &apps_smmu 0x1d84 0x1>, > + <0x500 &apps_smmu 0x1d85 0x1>, > + <0x600 &apps_smmu 0x1d86 0x1>, > + <0x700 &apps_smmu 0x1d87 0x1>, > + <0x800 &apps_smmu 0x1d88 0x1>, > + <0x900 &apps_smmu 0x1d89 0x1>, > + <0xa00 &apps_smmu 0x1d8a 0x1>, > + <0xb00 &apps_smmu 0x1d8b 0x1>, > + <0xc00 &apps_smmu 0x1d8c 0x1>, > + <0xd00 &apps_smmu 0x1d8d 0x1>, > + <0xe00 &apps_smmu 0x1d8e 0x1>, > + <0xf00 &apps_smmu 0x1d8f 0x1>; > > resets = <&gcc GCC_PCIE_0_BCR>; > reset-names = "pci"; > @@ -1909,9 +1923,23 @@ pcie1: pci@1c08000 { > assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; > assigned-clock-rates = <19200000>; > > - iommus = <&apps_smmu 0x1e00 0x7f>; > + iommus = <&apps_smmu 0x1e00 0xf>; > iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, > <0x100 &apps_smmu 0x1e01 0x1>; And here. Konrad > + <0x200 &apps_smmu 0x1e02 0x1>, > + <0x300 &apps_smmu 0x1e03 0x1>, > + <0x400 &apps_smmu 0x1e04 0x1>, > + <0x500 &apps_smmu 0x1e05 0x1>, > + <0x600 &apps_smmu 0x1e06 0x1>, > + <0x700 &apps_smmu 0x1e07 0x1>, > + <0x800 &apps_smmu 0x1e08 0x1>, > + <0x900 &apps_smmu 0x1e09 0x1>, > + <0xa00 &apps_smmu 0x1e0a 0x1>, > + <0xb00 &apps_smmu 0x1e0b 0x1>, > + <0xc00 &apps_smmu 0x1e0c 0x1>, > + <0xd00 &apps_smmu 0x1e0d 0x1>, > + <0xe00 &apps_smmu 0x1e0e 0x1>, > + <0xf00 &apps_smmu 0x1e0f 0x1>; > > resets = <&gcc GCC_PCIE_1_BCR>; > reset-names = "pci";
On Wed, 7 Dec 2022 at 09:29, Bhupesh Sharma <bhupesh.sharma@linaro.org> wrote: > > Fix the iommu sid values for the PCIe nodes present on > Qualcomm SM8150 SoC dtsi (in sync the with downstream code). The commit message describes what you did, not why. Is there any actual issue that you are trying to solve? It makes me wonder because all modern Qualcomm platforms share more or less the same setup. > > Fixes: a1c86c680533 ("arm64: dts: qcom: sm8150: Add PCIe nodes") > Cc: Bjorn Andersson <andersson@kernel.org> > Cc: Rob Herring <robh+dt@kernel.org> No need to have regular maintainers in Cc tags. Please use regular git-send-email arguments instead. > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8150.dtsi | 32 ++++++++++++++++++++++++++-- > 1 file changed, 30 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi > index d1b64280ab0b..e88d1617a1ab 100644 > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi > @@ -1810,9 +1810,23 @@ pcie0: pci@1c00000 { > "slave_q2a", > "tbu"; > > - iommus = <&apps_smmu 0x1d80 0x7f>; > + iommus = <&apps_smmu 0x1d80 0xf>; > iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, > <0x100 &apps_smmu 0x1d81 0x1>; it looks like the patch was not even compile-tested. > + <0x200 &apps_smmu 0x1d82 0x1>, > + <0x300 &apps_smmu 0x1d83 0x1>, > + <0x400 &apps_smmu 0x1d84 0x1>, > + <0x500 &apps_smmu 0x1d85 0x1>, > + <0x600 &apps_smmu 0x1d86 0x1>, > + <0x700 &apps_smmu 0x1d87 0x1>, > + <0x800 &apps_smmu 0x1d88 0x1>, > + <0x900 &apps_smmu 0x1d89 0x1>, > + <0xa00 &apps_smmu 0x1d8a 0x1>, > + <0xb00 &apps_smmu 0x1d8b 0x1>, > + <0xc00 &apps_smmu 0x1d8c 0x1>, > + <0xd00 &apps_smmu 0x1d8d 0x1>, > + <0xe00 &apps_smmu 0x1d8e 0x1>, > + <0xf00 &apps_smmu 0x1d8f 0x1>; > > resets = <&gcc GCC_PCIE_0_BCR>; > reset-names = "pci"; > @@ -1909,9 +1923,23 @@ pcie1: pci@1c08000 { > assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; > assigned-clock-rates = <19200000>; > > - iommus = <&apps_smmu 0x1e00 0x7f>; > + iommus = <&apps_smmu 0x1e00 0xf>; > iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, > <0x100 &apps_smmu 0x1e01 0x1>; > + <0x200 &apps_smmu 0x1e02 0x1>, > + <0x300 &apps_smmu 0x1e03 0x1>, > + <0x400 &apps_smmu 0x1e04 0x1>, > + <0x500 &apps_smmu 0x1e05 0x1>, > + <0x600 &apps_smmu 0x1e06 0x1>, > + <0x700 &apps_smmu 0x1e07 0x1>, > + <0x800 &apps_smmu 0x1e08 0x1>, > + <0x900 &apps_smmu 0x1e09 0x1>, > + <0xa00 &apps_smmu 0x1e0a 0x1>, > + <0xb00 &apps_smmu 0x1e0b 0x1>, > + <0xc00 &apps_smmu 0x1e0c 0x1>, > + <0xd00 &apps_smmu 0x1e0d 0x1>, > + <0xe00 &apps_smmu 0x1e0e 0x1>, > + <0xf00 &apps_smmu 0x1e0f 0x1>; > > resets = <&gcc GCC_PCIE_1_BCR>; > reset-names = "pci"; > -- > 2.38.1 >
On Thu, 8 Dec 2022 at 15:25, Konrad Dybcio <konrad.dybcio@linaro.org> wrote: > > > > On 07/12/2022 07:29, Bhupesh Sharma wrote: > > Fix the iommu sid values for the PCIe nodes present on > > Qualcomm SM8150 SoC dtsi (in sync the with downstream code). > > > > Fixes: a1c86c680533 ("arm64: dts: qcom: sm8150: Add PCIe nodes") > > Cc: Bjorn Andersson <andersson@kernel.org> > > Cc: Rob Herring <robh+dt@kernel.org> > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/sm8150.dtsi | 32 ++++++++++++++++++++++++++-- > > 1 file changed, 30 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi > > index d1b64280ab0b..e88d1617a1ab 100644 > > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi > > @@ -1810,9 +1810,23 @@ pcie0: pci@1c00000 { > > "slave_q2a", > > "tbu"; > > > > - iommus = <&apps_smmu 0x1d80 0x7f>; > > + iommus = <&apps_smmu 0x1d80 0xf>; > > iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, > > <0x100 &apps_smmu 0x1d81 0x1>; > Should be a "," here. > > > > + <0x200 &apps_smmu 0x1d82 0x1>, > > + <0x300 &apps_smmu 0x1d83 0x1>, > > + <0x400 &apps_smmu 0x1d84 0x1>, > > + <0x500 &apps_smmu 0x1d85 0x1>, > > + <0x600 &apps_smmu 0x1d86 0x1>, > > + <0x700 &apps_smmu 0x1d87 0x1>, > > + <0x800 &apps_smmu 0x1d88 0x1>, > > + <0x900 &apps_smmu 0x1d89 0x1>, > > + <0xa00 &apps_smmu 0x1d8a 0x1>, > > + <0xb00 &apps_smmu 0x1d8b 0x1>, > > + <0xc00 &apps_smmu 0x1d8c 0x1>, > > + <0xd00 &apps_smmu 0x1d8d 0x1>, > > + <0xe00 &apps_smmu 0x1d8e 0x1>, > > + <0xf00 &apps_smmu 0x1d8f 0x1>; > > > > resets = <&gcc GCC_PCIE_0_BCR>; > > reset-names = "pci"; > > @@ -1909,9 +1923,23 @@ pcie1: pci@1c08000 { > > assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; > > assigned-clock-rates = <19200000>; > > > > - iommus = <&apps_smmu 0x1e00 0x7f>; > > + iommus = <&apps_smmu 0x1e00 0xf>; > > iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, > > <0x100 &apps_smmu 0x1e01 0x1>; > And here. Oops. Thanks for noticing this. I will send a v2, Konrad. Thanks, Bhupesh > Konrad > > + <0x200 &apps_smmu 0x1e02 0x1>, > > + <0x300 &apps_smmu 0x1e03 0x1>, > > + <0x400 &apps_smmu 0x1e04 0x1>, > > + <0x500 &apps_smmu 0x1e05 0x1>, > > + <0x600 &apps_smmu 0x1e06 0x1>, > > + <0x700 &apps_smmu 0x1e07 0x1>, > > + <0x800 &apps_smmu 0x1e08 0x1>, > > + <0x900 &apps_smmu 0x1e09 0x1>, > > + <0xa00 &apps_smmu 0x1e0a 0x1>, > > + <0xb00 &apps_smmu 0x1e0b 0x1>, > > + <0xc00 &apps_smmu 0x1e0c 0x1>, > > + <0xd00 &apps_smmu 0x1e0d 0x1>, > > + <0xe00 &apps_smmu 0x1e0e 0x1>, > > + <0xf00 &apps_smmu 0x1e0f 0x1>; > > > > resets = <&gcc GCC_PCIE_1_BCR>; > > reset-names = "pci";
On Thu, 8 Dec 2022 at 16:14, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote: > > On Wed, 7 Dec 2022 at 09:29, Bhupesh Sharma <bhupesh.sharma@linaro.org> wrote: > > > > Fix the iommu sid values for the PCIe nodes present on > > Qualcomm SM8150 SoC dtsi (in sync the with downstream code). > > The commit message describes what you did, not why. Is there any > actual issue that you are trying to solve? Right, I will add that in v2. We have a customer facing some sid related IOMMU transactional errors on sm8150 based boards. > It makes me wonder because all modern Qualcomm platforms share more or > less the same setup. Please see sdm845.dtsi, which does the same as suggested via this patch for sm8150. Thanks, Bhupesh > > Fixes: a1c86c680533 ("arm64: dts: qcom: sm8150: Add PCIe nodes") > > Cc: Bjorn Andersson <andersson@kernel.org> > > Cc: Rob Herring <robh+dt@kernel.org> > > No need to have regular maintainers in Cc tags. Please use regular > git-send-email arguments instead. > > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/sm8150.dtsi | 32 ++++++++++++++++++++++++++-- > > 1 file changed, 30 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi > > index d1b64280ab0b..e88d1617a1ab 100644 > > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi > > @@ -1810,9 +1810,23 @@ pcie0: pci@1c00000 { > > "slave_q2a", > > "tbu"; > > > > - iommus = <&apps_smmu 0x1d80 0x7f>; > > + iommus = <&apps_smmu 0x1d80 0xf>; > > iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, > > <0x100 &apps_smmu 0x1d81 0x1>; > > it looks like the patch was not even compile-tested. > > > + <0x200 &apps_smmu 0x1d82 0x1>, > > + <0x300 &apps_smmu 0x1d83 0x1>, > > + <0x400 &apps_smmu 0x1d84 0x1>, > > + <0x500 &apps_smmu 0x1d85 0x1>, > > + <0x600 &apps_smmu 0x1d86 0x1>, > > + <0x700 &apps_smmu 0x1d87 0x1>, > > + <0x800 &apps_smmu 0x1d88 0x1>, > > + <0x900 &apps_smmu 0x1d89 0x1>, > > + <0xa00 &apps_smmu 0x1d8a 0x1>, > > + <0xb00 &apps_smmu 0x1d8b 0x1>, > > + <0xc00 &apps_smmu 0x1d8c 0x1>, > > + <0xd00 &apps_smmu 0x1d8d 0x1>, > > + <0xe00 &apps_smmu 0x1d8e 0x1>, > > + <0xf00 &apps_smmu 0x1d8f 0x1>; > > > > resets = <&gcc GCC_PCIE_0_BCR>; > > reset-names = "pci"; > > @@ -1909,9 +1923,23 @@ pcie1: pci@1c08000 { > > assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; > > assigned-clock-rates = <19200000>; > > > > - iommus = <&apps_smmu 0x1e00 0x7f>; > > + iommus = <&apps_smmu 0x1e00 0xf>; > > iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, > > <0x100 &apps_smmu 0x1e01 0x1>; > > + <0x200 &apps_smmu 0x1e02 0x1>, > > + <0x300 &apps_smmu 0x1e03 0x1>, > > + <0x400 &apps_smmu 0x1e04 0x1>, > > + <0x500 &apps_smmu 0x1e05 0x1>, > > + <0x600 &apps_smmu 0x1e06 0x1>, > > + <0x700 &apps_smmu 0x1e07 0x1>, > > + <0x800 &apps_smmu 0x1e08 0x1>, > > + <0x900 &apps_smmu 0x1e09 0x1>, > > + <0xa00 &apps_smmu 0x1e0a 0x1>, > > + <0xb00 &apps_smmu 0x1e0b 0x1>, > > + <0xc00 &apps_smmu 0x1e0c 0x1>, > > + <0xd00 &apps_smmu 0x1e0d 0x1>, > > + <0xe00 &apps_smmu 0x1e0e 0x1>, > > + <0xf00 &apps_smmu 0x1e0f 0x1>; > > > > resets = <&gcc GCC_PCIE_1_BCR>; > > reset-names = "pci"; > > -- > > 2.38.1 > > > > > -- > With best wishes > Dmitry
On Thu, 8 Dec 2022 at 14:05, Bhupesh Sharma <bhupesh.sharma@linaro.org> wrote: > > On Thu, 8 Dec 2022 at 16:14, Dmitry Baryshkov > <dmitry.baryshkov@linaro.org> wrote: > > > > On Wed, 7 Dec 2022 at 09:29, Bhupesh Sharma <bhupesh.sharma@linaro.org> wrote: > > > > > > Fix the iommu sid values for the PCIe nodes present on > > > Qualcomm SM8150 SoC dtsi (in sync the with downstream code). > > > > The commit message describes what you did, not why. Is there any > > actual issue that you are trying to solve? > > Right, I will add that in v2. We have a customer facing some sid > related IOMMU transactional errors on sm8150 based boards. > > > It makes me wonder because all modern Qualcomm platforms share more or > > less the same setup. > > Please see sdm845.dtsi, which does the same as suggested via this > patch for sm8150. Should we also apply the same change to other platforms? > > Thanks, > Bhupesh > > > > Fixes: a1c86c680533 ("arm64: dts: qcom: sm8150: Add PCIe nodes") > > > Cc: Bjorn Andersson <andersson@kernel.org> > > > Cc: Rob Herring <robh+dt@kernel.org> > > > > No need to have regular maintainers in Cc tags. Please use regular > > git-send-email arguments instead. > > > > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > > > --- > > > arch/arm64/boot/dts/qcom/sm8150.dtsi | 32 ++++++++++++++++++++++++++-- > > > 1 file changed, 30 insertions(+), 2 deletions(-) > > > > > > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi > > > index d1b64280ab0b..e88d1617a1ab 100644 > > > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi > > > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi > > > @@ -1810,9 +1810,23 @@ pcie0: pci@1c00000 { > > > "slave_q2a", > > > "tbu"; > > > > > > - iommus = <&apps_smmu 0x1d80 0x7f>; > > > + iommus = <&apps_smmu 0x1d80 0xf>; > > > iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, > > > <0x100 &apps_smmu 0x1d81 0x1>; > > > > it looks like the patch was not even compile-tested. > > > > > + <0x200 &apps_smmu 0x1d82 0x1>, > > > + <0x300 &apps_smmu 0x1d83 0x1>, > > > + <0x400 &apps_smmu 0x1d84 0x1>, > > > + <0x500 &apps_smmu 0x1d85 0x1>, > > > + <0x600 &apps_smmu 0x1d86 0x1>, > > > + <0x700 &apps_smmu 0x1d87 0x1>, > > > + <0x800 &apps_smmu 0x1d88 0x1>, > > > + <0x900 &apps_smmu 0x1d89 0x1>, > > > + <0xa00 &apps_smmu 0x1d8a 0x1>, > > > + <0xb00 &apps_smmu 0x1d8b 0x1>, > > > + <0xc00 &apps_smmu 0x1d8c 0x1>, > > > + <0xd00 &apps_smmu 0x1d8d 0x1>, > > > + <0xe00 &apps_smmu 0x1d8e 0x1>, > > > + <0xf00 &apps_smmu 0x1d8f 0x1>; > > > > > > resets = <&gcc GCC_PCIE_0_BCR>; > > > reset-names = "pci"; > > > @@ -1909,9 +1923,23 @@ pcie1: pci@1c08000 { > > > assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; > > > assigned-clock-rates = <19200000>; > > > > > > - iommus = <&apps_smmu 0x1e00 0x7f>; > > > + iommus = <&apps_smmu 0x1e00 0xf>; > > > iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, > > > <0x100 &apps_smmu 0x1e01 0x1>; > > > + <0x200 &apps_smmu 0x1e02 0x1>, > > > + <0x300 &apps_smmu 0x1e03 0x1>, > > > + <0x400 &apps_smmu 0x1e04 0x1>, > > > + <0x500 &apps_smmu 0x1e05 0x1>, > > > + <0x600 &apps_smmu 0x1e06 0x1>, > > > + <0x700 &apps_smmu 0x1e07 0x1>, > > > + <0x800 &apps_smmu 0x1e08 0x1>, > > > + <0x900 &apps_smmu 0x1e09 0x1>, > > > + <0xa00 &apps_smmu 0x1e0a 0x1>, > > > + <0xb00 &apps_smmu 0x1e0b 0x1>, > > > + <0xc00 &apps_smmu 0x1e0c 0x1>, > > > + <0xd00 &apps_smmu 0x1e0d 0x1>, > > > + <0xe00 &apps_smmu 0x1e0e 0x1>, > > > + <0xf00 &apps_smmu 0x1e0f 0x1>; > > > > > > resets = <&gcc GCC_PCIE_1_BCR>; > > > reset-names = "pci"; > > > -- > > > 2.38.1 > > > > > > > > > -- > > With best wishes > > Dmitry
On Thu, 8 Dec 2022 at 19:43, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote: > > On Thu, 8 Dec 2022 at 14:05, Bhupesh Sharma <bhupesh.sharma@linaro.org> wrote: > > > > On Thu, 8 Dec 2022 at 16:14, Dmitry Baryshkov > > <dmitry.baryshkov@linaro.org> wrote: > > > > > > On Wed, 7 Dec 2022 at 09:29, Bhupesh Sharma <bhupesh.sharma@linaro.org> wrote: > > > > > > > > Fix the iommu sid values for the PCIe nodes present on > > > > Qualcomm SM8150 SoC dtsi (in sync the with downstream code). > > > > > > The commit message describes what you did, not why. Is there any > > > actual issue that you are trying to solve? > > > > Right, I will add that in v2. We have a customer facing some sid > > related IOMMU transactional errors on sm8150 based boards. > > > > > It makes me wonder because all modern Qualcomm platforms share more or > > > less the same setup. > > > > Please see sdm845.dtsi, which does the same as suggested via this > > patch for sm8150. > > Should we also apply the same change to other platforms? That's a good question. But I have no test data points to say that this should be valid for other platforms as well. Let me check with the folks @ qcom who reported this, (i.e. whether they see this with other qcom platforms as well), but let's not hold back this fix while we wait for more data. Thanks. > > > > Fixes: a1c86c680533 ("arm64: dts: qcom: sm8150: Add PCIe nodes") > > > > Cc: Bjorn Andersson <andersson@kernel.org> > > > > Cc: Rob Herring <robh+dt@kernel.org> > > > > > > No need to have regular maintainers in Cc tags. Please use regular > > > git-send-email arguments instead. > > > > > > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > > > > --- > > > > arch/arm64/boot/dts/qcom/sm8150.dtsi | 32 ++++++++++++++++++++++++++-- > > > > 1 file changed, 30 insertions(+), 2 deletions(-) > > > > > > > > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi > > > > index d1b64280ab0b..e88d1617a1ab 100644 > > > > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi > > > > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi > > > > @@ -1810,9 +1810,23 @@ pcie0: pci@1c00000 { > > > > "slave_q2a", > > > > "tbu"; > > > > > > > > - iommus = <&apps_smmu 0x1d80 0x7f>; > > > > + iommus = <&apps_smmu 0x1d80 0xf>; > > > > iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, > > > > <0x100 &apps_smmu 0x1d81 0x1>; > > > > > > it looks like the patch was not even compile-tested. > > > > > > > + <0x200 &apps_smmu 0x1d82 0x1>, > > > > + <0x300 &apps_smmu 0x1d83 0x1>, > > > > + <0x400 &apps_smmu 0x1d84 0x1>, > > > > + <0x500 &apps_smmu 0x1d85 0x1>, > > > > + <0x600 &apps_smmu 0x1d86 0x1>, > > > > + <0x700 &apps_smmu 0x1d87 0x1>, > > > > + <0x800 &apps_smmu 0x1d88 0x1>, > > > > + <0x900 &apps_smmu 0x1d89 0x1>, > > > > + <0xa00 &apps_smmu 0x1d8a 0x1>, > > > > + <0xb00 &apps_smmu 0x1d8b 0x1>, > > > > + <0xc00 &apps_smmu 0x1d8c 0x1>, > > > > + <0xd00 &apps_smmu 0x1d8d 0x1>, > > > > + <0xe00 &apps_smmu 0x1d8e 0x1>, > > > > + <0xf00 &apps_smmu 0x1d8f 0x1>; > > > > > > > > resets = <&gcc GCC_PCIE_0_BCR>; > > > > reset-names = "pci"; > > > > @@ -1909,9 +1923,23 @@ pcie1: pci@1c08000 { > > > > assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; > > > > assigned-clock-rates = <19200000>; > > > > > > > > - iommus = <&apps_smmu 0x1e00 0x7f>; > > > > + iommus = <&apps_smmu 0x1e00 0xf>; > > > > iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, > > > > <0x100 &apps_smmu 0x1e01 0x1>; > > > > + <0x200 &apps_smmu 0x1e02 0x1>, > > > > + <0x300 &apps_smmu 0x1e03 0x1>, > > > > + <0x400 &apps_smmu 0x1e04 0x1>, > > > > + <0x500 &apps_smmu 0x1e05 0x1>, > > > > + <0x600 &apps_smmu 0x1e06 0x1>, > > > > + <0x700 &apps_smmu 0x1e07 0x1>, > > > > + <0x800 &apps_smmu 0x1e08 0x1>, > > > > + <0x900 &apps_smmu 0x1e09 0x1>, > > > > + <0xa00 &apps_smmu 0x1e0a 0x1>, > > > > + <0xb00 &apps_smmu 0x1e0b 0x1>, > > > > + <0xc00 &apps_smmu 0x1e0c 0x1>, > > > > + <0xd00 &apps_smmu 0x1e0d 0x1>, > > > > + <0xe00 &apps_smmu 0x1e0e 0x1>, > > > > + <0xf00 &apps_smmu 0x1e0f 0x1>; > > > > > > > > resets = <&gcc GCC_PCIE_1_BCR>; > > > > reset-names = "pci"; > > > > -- > > > > 2.38.1 > > > > > > > > > > > > > -- > > > With best wishes > > > Dmitry > > > > -- > With best wishes > Dmitry
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index d1b64280ab0b..e88d1617a1ab 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1810,9 +1810,23 @@ pcie0: pci@1c00000 { "slave_q2a", "tbu"; - iommus = <&apps_smmu 0x1d80 0x7f>; + iommus = <&apps_smmu 0x1d80 0xf>; iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, <0x100 &apps_smmu 0x1d81 0x1>; + <0x200 &apps_smmu 0x1d82 0x1>, + <0x300 &apps_smmu 0x1d83 0x1>, + <0x400 &apps_smmu 0x1d84 0x1>, + <0x500 &apps_smmu 0x1d85 0x1>, + <0x600 &apps_smmu 0x1d86 0x1>, + <0x700 &apps_smmu 0x1d87 0x1>, + <0x800 &apps_smmu 0x1d88 0x1>, + <0x900 &apps_smmu 0x1d89 0x1>, + <0xa00 &apps_smmu 0x1d8a 0x1>, + <0xb00 &apps_smmu 0x1d8b 0x1>, + <0xc00 &apps_smmu 0x1d8c 0x1>, + <0xd00 &apps_smmu 0x1d8d 0x1>, + <0xe00 &apps_smmu 0x1d8e 0x1>, + <0xf00 &apps_smmu 0x1d8f 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; @@ -1909,9 +1923,23 @@ pcie1: pci@1c08000 { assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; - iommus = <&apps_smmu 0x1e00 0x7f>; + iommus = <&apps_smmu 0x1e00 0xf>; iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, <0x100 &apps_smmu 0x1e01 0x1>; + <0x200 &apps_smmu 0x1e02 0x1>, + <0x300 &apps_smmu 0x1e03 0x1>, + <0x400 &apps_smmu 0x1e04 0x1>, + <0x500 &apps_smmu 0x1e05 0x1>, + <0x600 &apps_smmu 0x1e06 0x1>, + <0x700 &apps_smmu 0x1e07 0x1>, + <0x800 &apps_smmu 0x1e08 0x1>, + <0x900 &apps_smmu 0x1e09 0x1>, + <0xa00 &apps_smmu 0x1e0a 0x1>, + <0xb00 &apps_smmu 0x1e0b 0x1>, + <0xc00 &apps_smmu 0x1e0c 0x1>, + <0xd00 &apps_smmu 0x1e0d 0x1>, + <0xe00 &apps_smmu 0x1e0e 0x1>, + <0xf00 &apps_smmu 0x1e0f 0x1>; resets = <&gcc GCC_PCIE_1_BCR>; reset-names = "pci";
Fix the iommu sid values for the PCIe nodes present on Qualcomm SM8150 SoC dtsi (in sync the with downstream code). Fixes: a1c86c680533 ("arm64: dts: qcom: sm8150: Add PCIe nodes") Cc: Bjorn Andersson <andersson@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 32 ++++++++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-)