| Message ID | 08e8dc0f58145915f19d953c487a0df20a1ced1f.1672148732.git.quic_schowdhu@quicinc.com |
|---|---|
| State | Accepted |
| Commit | add74cad7c9d1bf59d41b229852f3ebe0be4a84f |
| Headers | show |
| Series | [V21,1/7] dt-bindings: soc: qcom,dcc: Add the dtschema | expand |
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 58976a1..3b1bcad 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2089,6 +2089,12 @@ #power-domain-cells = <1>; }; + dma@10a2000 { + compatible = "qcom,sc7180-dcc", "qcom,dcc"; + reg = <0x0 0x010a2000 0x0 0x1000>, + <0x0 0x010ae000 0x0 0x2000>; + }; + stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0 0x06002000 0 0x1000>,
Add the DCC(Data Capture and Compare) device tree node entry along with the address of the register region. Signed-off-by: Souradeep Chowdhury <quic_schowdhu@quicinc.com> --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)