| Message ID | 20230104180513.1379453-3-conor@kernel.org |
|---|---|
| State | New |
| Headers | show |
| Series | None | expand |
On Wed, 04 Jan 2023 18:05:14 +0000, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > Since commit 03f11f03dbfe ("RISC-V: Parse cpu topology during boot.") > RISC-V has used the generic arch topology code, which provides for > disparate CPU capacities. We never defined a binding to acquire this > information from the DT though, so document the one already used by the > generic arch topology code: "capacity-dmips-mhz". > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > Acked-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index c6720764e765..2480c2460759 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -114,6 +114,12 @@ properties: List of phandles to idle state nodes supported by this hart (see ./idle-states.yaml). + capacity-dmips-mhz: + description: + u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in + DMIPS/MHz, relative to highest capacity-dmips-mhz + in the system. + required: - riscv,isa - interrupt-controller