diff mbox series

riscv: dts: fu740: fix size of pcie 32bit memory

Message ID 20230106134456.265891-1-ben.dooks@codethink.co.uk
State Accepted
Commit 43d5f5d63699724d47f0d9e0eae516a260d232b4
Headers show
Series riscv: dts: fu740: fix size of pcie 32bit memory | expand

Commit Message

Ben Dooks Jan. 6, 2023, 1:44 p.m. UTC
The 32-bit memory resource is needed for non-prefetchable memory
allocations on the PCIe bus, however with some cards (such as the
SM768) the system fails to allocate memory from this.

Checking the allocation against the datasheet, it looks like there
has been a mis-calcualation of the resource for the first memory
region (0x0060090000..0x0070ffffff) which in the data-sheet for
the fu740 (v1p2) is from 0x0060000000..0x007fffffff. Changing
this to allocate from 0x0060090000..0x007fffffff fixes the probing
issues.

Fixes: ae80d514808557018e44190 ("riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC
")

Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
Note, this is probably a stable candiate as it looks like it has
been this way since it was commited.
---
 arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Krzysztof Kozlowski Jan. 6, 2023, 2:07 p.m. UTC | #1
On 06/01/2023 14:44, Ben Dooks wrote:
> The 32-bit memory resource is needed for non-prefetchable memory
> allocations on the PCIe bus, however with some cards (such as the
> SM768) the system fails to allocate memory from this.
> 
> Checking the allocation against the datasheet, it looks like there
> has been a mis-calcualation of the resource for the first memory
> region (0x0060090000..0x0070ffffff) which in the data-sheet for
> the fu740 (v1p2) is from 0x0060000000..0x007fffffff. Changing
> this to allocate from 0x0060090000..0x007fffffff fixes the probing
> issues.
> 
> Fixes: ae80d514808557018e44190 ("riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC
> ")

Don't wrap lines.

> 

Drop empty line between tags.

> Cc: Paul Walmsley <paul.walmsley@sifive.com>
> Cc: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> ---

Best regards,
Krzysztof
Ben Dooks Jan. 6, 2023, 2:52 p.m. UTC | #2
On 06/01/2023 14:51, Ben Dooks wrote:
> On 06/01/2023 14:07, Krzysztof Kozlowski wrote:
>> On 06/01/2023 14:44, Ben Dooks wrote:
>>> The 32-bit memory resource is needed for non-prefetchable memory
>>> allocations on the PCIe bus, however with some cards (such as the
>>> SM768) the system fails to allocate memory from this.
>>>
>>> Checking the allocation against the datasheet, it looks like there
>>> has been a mis-calcualation of the resource for the first memory
>>> region (0x0060090000..0x0070ffffff) which in the data-sheet for
>>> the fu740 (v1p2) is from 0x0060000000..0x007fffffff. Changing
>>> this to allocate from 0x0060090000..0x007fffffff fixes the probing
>>> issues.
>>>
>>> Fixes: ae80d514808557018e44190 ("riscv: dts: Add PCIe support for the 
>>> SiFive FU740-C000 SoC
>>> ")
>>
>> Don't wrap lines.
>>
>>>
>>
>> Drop empty line between tags.
> 
> 
> Thanks, will fix.
> 
> Does anyone have a chance to review and/or test this, it works for me
> but I've not got a large number of devices to test with.

I forgot add that if a couple of other people can check this over then
I'll cc stable next time
Conor Dooley Jan. 6, 2023, 2:55 p.m. UTC | #3
On Fri, Jan 06, 2023 at 02:51:04PM +0000, Ben Dooks wrote:
> On 06/01/2023 14:07, Krzysztof Kozlowski wrote:
> > On 06/01/2023 14:44, Ben Dooks wrote:
> > > The 32-bit memory resource is needed for non-prefetchable memory
> > > allocations on the PCIe bus, however with some cards (such as the
> > > SM768) the system fails to allocate memory from this.
> > > 
> > > Checking the allocation against the datasheet, it looks like there
> > > has been a mis-calcualation of the resource for the first memory
> > > region (0x0060090000..0x0070ffffff) which in the data-sheet for
> > > the fu740 (v1p2) is from 0x0060000000..0x007fffffff. Changing
> > > this to allocate from 0x0060090000..0x007fffffff fixes the probing
> > > issues.
> > > 
> > > Fixes: ae80d514808557018e44190 ("riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC
> > > ")
> > 
> > Don't wrap lines.
> > 
> > > 
> > 
> > Drop empty line between tags.
> 
> 
> Thanks, will fix.

I wouldn't bother resending to fix that stuff, can be done on
application.

I don't have a PCI card handy to test with so +CC Ron, perhaps he can
give this patch a go.

I can give it a go next week though probably if nothing's come through -
although likely not with something like an SM768.

Thanks,
Conor.
Conor Dooley Jan. 7, 2023, 7:37 p.m. UTC | #4
From: Conor Dooley <conor.dooley@microchip.com>

On Fri, 06 Jan 2023 13:44:56 +0000, Ben Dooks wrote:
> The 32-bit memory resource is needed for non-prefetchable memory
> allocations on the PCIe bus, however with some cards (such as the
> SM768) the system fails to allocate memory from this.
> 
> Checking the allocation against the datasheet, it looks like there
> has been a mis-calcualation of the resource for the first memory
> region (0x0060090000..0x0070ffffff) which in the data-sheet for
> the fu740 (v1p2) is from 0x0060000000..0x007fffffff. Changing
> this to allocate from 0x0060090000..0x007fffffff fixes the probing
> issues.
> 
> [...]

Applied to riscv-dt-fixes, thanks!

[1/1] riscv: dts: fu740: fix size of pcie 32bit memory
	https://git.kernel.org/conor/c/43d5f5d63699724d47f0d9e0eae516a260d232b4

I checked the numbers and they look correct per the v1p2 doc.
I added a T-b from IRC for Ron, added the cc: stable and fixed the
fixes tag while I was at it.

Thanks,
Conor.
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
index 43bed6c0a84f..5235fd1c9cb6 100644
--- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
@@ -328,7 +328,7 @@  pcie@e00000000 {
 			bus-range = <0x0 0xff>;
 			ranges = <0x81000000  0x0 0x60080000  0x0 0x60080000 0x0 0x10000>,      /* I/O */
 				 <0x82000000  0x0 0x60090000  0x0 0x60090000 0x0 0xff70000>,    /* mem */
-				 <0x82000000  0x0 0x70000000  0x0 0x70000000 0x0 0x1000000>,    /* mem */
+				 <0x82000000  0x0 0x70000000  0x0 0x70000000 0x0 0x10000000>,    /* mem */
 				 <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>;  /* mem prefetchable */
 			num-lanes = <0x8>;
 			interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;