@@ -6,6 +6,7 @@
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/clk.h>
+#include <linux/clk-provider.h>
#include <linux/completion.h>
#include <linux/cpuidle.h>
#include <linux/debugfs.h>
@@ -323,6 +324,7 @@ static const u32 svs_regs_v2[] = {
* @bank_max: total number of svs banks
* @efuse: svs efuse data received from NVMEM framework
* @tefuse: thermal efuse data received from NVMEM framework
+ * @clk_cnt: clock count shows the clk enable/disable times by svs driver
*/
struct svs_platform {
void __iomem *base;
@@ -337,6 +339,7 @@ struct svs_platform {
u32 bank_max;
u32 *efuse;
u32 *tefuse;
+ s32 clk_cnt;
};
struct svs_platform_data {
@@ -496,6 +499,32 @@ static void svs_switch_bank(struct svs_platform *svsp)
svs_writel_relaxed(svsp, svsb->core_sel, CORESEL);
}
+static bool svs_is_clk_enabled(struct svs_platform *svsp)
+{
+ return svsp->clk_cnt > 0 ? true : false;
+}
+
+static int svs_clk_enable(struct svs_platform *svsp)
+{
+ int ret;
+
+ ret = clk_prepare_enable(svsp->main_clk);
+ if (ret) {
+ dev_err(svsp->dev, "cannot enable main_clk: %d\n", ret);
+ return ret;
+ }
+
+ svsp->clk_cnt++;
+
+ return 0;
+}
+
+static void svs_clk_disable(struct svs_platform *svsp)
+{
+ clk_disable_unprepare(svsp->main_clk);
+ svsp->clk_cnt--;
+}
+
static u32 svs_bank_volt_to_opp_volt(u32 svsb_volt, u32 svsb_volt_step,
u32 svsb_volt_base)
{
@@ -1543,6 +1572,12 @@ static int svs_suspend(struct device *dev)
int ret;
u32 idx;
+ if (!svs_is_clk_enabled(svsp)) {
+ dev_err(svsp->dev, "svs clk is disabled already (%d)\n",
+ svsp->clk_cnt);
+ return 0;
+ }
+
for (idx = 0; idx < svsp->bank_max; idx++) {
svsb = &svsp->banks[idx];
@@ -1564,7 +1599,7 @@ static int svs_suspend(struct device *dev)
return ret;
}
- clk_disable_unprepare(svsp->main_clk);
+ svs_clk_disable(svsp);
return 0;
}
@@ -1574,28 +1609,27 @@ static int svs_resume(struct device *dev)
struct svs_platform *svsp = dev_get_drvdata(dev);
int ret;
- ret = clk_prepare_enable(svsp->main_clk);
- if (ret) {
- dev_err(svsp->dev, "cannot enable main_clk, disable svs\n");
+ ret = svs_clk_enable(svsp);
+ if (ret)
return ret;
- }
ret = reset_control_deassert(svsp->rst);
if (ret) {
dev_err(svsp->dev, "cannot deassert reset %d\n", ret);
- goto out_of_resume;
+ goto svs_resume_clk_disable;
}
ret = svs_init02(svsp);
if (ret)
- goto out_of_resume;
+ goto svs_resume_clk_disable;
svs_mon_mode(svsp);
return 0;
-out_of_resume:
- clk_disable_unprepare(svsp->main_clk);
+svs_resume_clk_disable:
+ svs_clk_disable(svsp);
+
return ret;
}
@@ -2340,11 +2374,9 @@ static int svs_probe(struct platform_device *pdev)
goto svs_probe_free_tefuse;
}
- ret = clk_prepare_enable(svsp->main_clk);
- if (ret) {
- dev_err(svsp->dev, "cannot enable main clk: %d\n", ret);
+ ret = svs_clk_enable(svsp);
+ if (ret)
goto svs_probe_free_tefuse;
- }
svsp->base = of_iomap(svsp->dev->of_node, 0);
if (IS_ERR_OR_NULL(svsp->base)) {
@@ -2385,7 +2417,7 @@ static int svs_probe(struct platform_device *pdev)
iounmap(svsp->base);
svs_probe_clk_disable:
- clk_disable_unprepare(svsp->main_clk);
+ svs_clk_disable(svsp);
svs_probe_free_tefuse:
if (!IS_ERR_OR_NULL(svsp->tefuse))
In MediaTek HW design, svs and thermal both use the same clk source. It means that svs clk reference count from CCF includes thermal control counts. That makes svs driver confuse whether it disabled svs's main clk or not from CCF's perspective and lead to turn off their shared clk unexpectedly. Therefore, we add svs clk control APIs to make sure svs's main clk is controlled well by svs driver itself. Here is a NG example. Rely on CCF's reference count and cause problem. thermal probe (clk ref = 1) -> svs probe (clk ref = 2) -> svs suspend (clk ref = 1) -> thermal suspend (clk ref = 0) -> thermal resume (clk ref = 1) -> svs resume (encounter error, clk ref = 1) -> svs suspend (clk ref = 0) -> thermal suspend (Fail here, thermal HW control w/o clk) Signed-off-by: Roger Lu <roger.lu@mediatek.com> --- drivers/soc/mediatek/mtk-svs.c | 60 ++++++++++++++++++++++++++-------- 1 file changed, 46 insertions(+), 14 deletions(-)