| Message ID | 20230113142718.3038265-9-o.rempel@pengutronix.de |
|---|---|
| State | Accepted |
| Commit | 5417c655b98ed385d18695a9fbb384883a0d1f47 |
| Headers | show |
| Series | [v1,01/20] clk: imx: add clk-gpr-mux driver | expand |
Hi Oleksij, On Fri, Jan 13, 2023 at 11:27 AM Oleksij Rempel <o.rempel@pengutronix.de> wrote: > > Configure Ethernet reference clock parent in an obvious way instead of > using cryptic ptp way. Could you please improve the commit log? The "obvious way" is not obvious for people that don't have the board schematics. I like better the way you described the 20/20 patch: "On this board the PHY is the ref clock provider. So, configure ethernet reference clock as input." Please use this format globally in the series, as it becomes clear who is providing the ref clock. Thanks
diff --git a/arch/arm/boot/dts/imx6dl-plybas.dts b/arch/arm/boot/dts/imx6dl-plybas.dts index c52e6caf3996..e98046eea7a4 100644 --- a/arch/arm/boot/dts/imx6dl-plybas.dts +++ b/arch/arm/boot/dts/imx6dl-plybas.dts @@ -75,6 +75,7 @@ clk50m_phy: phy-clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <50000000>; + clock-output-names = "enet_ref_pad"; }; reg_5v0: regulator-5v0 { @@ -99,6 +100,13 @@ &can2 { status = "okay"; }; +&clks { + clocks = <&clk50m_phy>; + clock-names = "enet_ref_pad"; + assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; + assigned-clock-parents = <&clk50m_phy>; +}; + &ecspi1 { cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -116,10 +124,6 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rmii"; - clocks = <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>, - <&clk50m_phy>; - clock-names = "ipg", "ahb", "ptp"; phy-handle = <&rgmii_phy>; status = "okay";
Configure Ethernet reference clock parent in an obvious way instead of using cryptic ptp way. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> --- arch/arm/boot/dts/imx6dl-plybas.dts | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)