diff mbox series

[v2,01/14] qcs404: sysmap: Don't map reserved memory ranges

Message ID 20230201135901.482671-2-sumit.garg@linaro.org
State Accepted
Commit 881338a0c6686bbcf043275714d43080b746b17e
Headers show
Series QCS404: Add ethernet and I2C drivers | expand

Commit Message

Sumit Garg Feb. 1, 2023, 1:58 p.m. UTC
Currently u-boot maps whole of 1G RAM but there reserved memory ranges on
QCS404 which are reserved for TrustZone, various firmware components etc.
Any access to these reserved memory ranges causes a bus hang issue. So
disable mapping for reserved memory ranges in u-boot.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
 arch/arm/mach-snapdragon/sysmap-qcs404.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

Comments

Tom Rini Feb. 10, 2023, 6:43 p.m. UTC | #1
On Wed, Feb 01, 2023 at 07:28:48PM +0530, Sumit Garg wrote:

> Currently u-boot maps whole of 1G RAM but there reserved memory ranges on
> QCS404 which are reserved for TrustZone, various firmware components etc.
> Any access to these reserved memory ranges causes a bus hang issue. So
> disable mapping for reserved memory ranges in u-boot.
> 
> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

Applied to u-boot/master, thanks!
diff mbox series

Patch

diff --git a/arch/arm/mach-snapdragon/sysmap-qcs404.c b/arch/arm/mach-snapdragon/sysmap-qcs404.c
index b7409031a0..64ca4adf1b 100644
--- a/arch/arm/mach-snapdragon/sysmap-qcs404.c
+++ b/arch/arm/mach-snapdragon/sysmap-qcs404.c
@@ -19,7 +19,19 @@  static struct mm_region qcs404_mem_map[] = {
 	}, {
 		.virt = 0x80000000UL, /* DDR */
 		.phys = 0x80000000UL, /* DDR */
-		.size = 0x40000000UL,
+		.size = 0x05900000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0x89600000UL, /* DDR */
+		.phys = 0x89600000UL, /* DDR */
+		.size = 0x162000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0xa0000000UL, /* DDR */
+		.phys = 0xa0000000UL, /* DDR */
+		.size = 0x20000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_INNER_SHARE
 	}, {