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[v3,4/7] dt-bindings: PCI: dwc: add DMA, region mask bits

Message ID 20230223180531.15148-5-enachman@marvell.com
State New
Headers show
Series PCI: dwc: Add support for Marvell AC5 SoC | expand

Commit Message

Elad Nachman Feb. 23, 2023, 6:05 p.m. UTC 
From: Elad Nachman <enachman@marvell.com>

Add properties to support configurable DMA mask bits
and region mask bits.
configurable DMA mask bits is needed for Marvell AC5/AC5X SOCs which
have their physical DDR memory start at address 0x2_0000_0000.
Configurable region mask bits is needed for the Marvell Armada
7020/7040/8040 SOCs when the DT file places the PCIe window above the
4GB region.
The Synopsis Designware PCIe IP in these SOCs is too old to specify the
highest memory location supported by the PCIe, but practically supports
such locations. Allow these locations to be specified in the DT file.
First DT property is called num-dmamask,
and can range between 33 and 64.
Second DT property is called num-regionmask,
and can range between 33 and 64.

Signed-off-by: Elad Nachman <enachman@marvell.com>
---
 .../devicetree/bindings/pci/snps,dw-pcie-common.yaml   | 10 ++++++++++
 1 file changed, 10 insertions(+)
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Patch

diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
index d87e13496834..a1b06ff19ca7 100644
--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
@@ -261,6 +261,16 @@  properties:
 
   dma-coherent: true
 
+  num-dmamask:
+    description: |
+      number of dma mask bits to use, if different than default 32
+    maximum: 64
+
+  num-regionmask:
+    description: |
+      number of region limit mask bits to use, if different than default 32
+    maximum: 64
+
 additionalProperties: true
 
 ...