@@ -245,13 +245,18 @@
status = "okay";
};
-&qpic_bam {
+&pcie_phy {
+ vdda-phy-supply = <&vreg_l1b_1p2>;
+ vdda-pll-supply = <&vreg_l4b_0p88>;
+
status = "okay";
};
-&qpic_nand {
+&qpic_bam {
status = "okay";
+};
+&qpic_nand {
nand@0 {
reg = <0>;
@@ -262,11 +267,14 @@
secure-regions = /bits/ 64 <0x500000 0x500000
0xa00000 0xb00000>;
};
+
+ status = "okay";
};
&remoteproc_mpss {
- status = "okay";
memory-region = <&mpss_adsp_mem>;
+
+ status = "okay";
};
&usb {
@@ -278,14 +286,16 @@
};
&usb_hsphy {
- status = "okay";
vdda-pll-supply = <&vreg_l4b_0p88>;
vdda33-supply = <&vreg_l10b_3p08>;
vdda18-supply = <&vreg_l5b_1p8>;
+
+ status = "okay";
};
&usb_qmpphy {
- status = "okay";
vdda-phy-supply = <&vreg_l4b_0p88>;
vdda-pll-supply = <&vreg_l1b_1p2>;
+
+ status = "okay";
};
Enable PCIe PHY on SDX65 MTP for PCIe EP. While at it, updating status as last property for each node. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-)