diff mbox

[edk2,2/6] OvmfPkg: add and use industry standard macro PIIX4_PMBA_MASK

Message ID 1462840655-1802-3-git-send-email-lersek@redhat.com
State New
Headers show

Commit Message

Laszlo Ersek May 10, 2016, 12:37 a.m. UTC 
We already have the identical purpose (but different value) macro for
ICH9, namely ICH9_PMBASE_MASK in
"OvmfPkg/Include/IndustryStandard/Q35MchIch9.h".

Also, stop bit-negating signed integer constants.

Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1333238
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>

---
 OvmfPkg/Include/IndustryStandard/I440FxPiix4.h     | 2 ++
 OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c    | 2 +-
 OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c | 2 +-
 OvmfPkg/PlatformPei/Platform.c                     | 2 +-
 4 files changed, 5 insertions(+), 3 deletions(-)

-- 
1.8.3.1


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diff mbox

Patch

diff --git a/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h b/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h
index 8cbd685ab509..baa4c063f16a 100644
--- a/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h
+++ b/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h
@@ -31,10 +31,12 @@ 
 // B/D/F/Type: 0/1/3/PCI
 //
 #define POWER_MGMT_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 1, 3, (Offset))
 
 #define PIIX4_PMBA             0x40
+#define PIIX4_PMBA_MASK          (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \
+                                  BIT10 | BIT9  | BIT8  | BIT7  | BIT6)
 
 #define PIIX4_PMREGMISC        0x80
 #define PIIX4_PMREGMISC_PMIOSE   BIT0
 
 #endif
diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
index f722731ca4f6..e85f18f8090d 100644
--- a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
@@ -71,11 +71,11 @@  AcpiTimerLibConstructor (
   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
     //
     // If the Power Management Base Address is not programmed,
     // then program the Power Management Base Address from a PCD.
     //
-    PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0,
+    PciAndThenOr32 (Pmba, ~(UINT32)PIIX4_PMBA_MASK,
       FixedPcdGet16 (PcdPiix4AcpiPmBaseAddress));
 
     //
     // Enable PMBA I/O port decodes
     //
diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
index b0ab783843a8..52eaaf0ad339 100644
--- a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
@@ -67,11 +67,11 @@  AcpiTimerLibConstructor (
   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
     //
     // If the Power Management Base Address is not programmed,
     // then program the Power Management Base Address from a PCD.
     //
-    PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0,
+    PciAndThenOr32 (Pmba, ~(UINT32)PIIX4_PMBA_MASK,
       FixedPcdGet16 (PcdPiix4AcpiPmBaseAddress));
 
     //
     // Enable PMBA I/O port decodes
     //
diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index e4e21da5aa9b..a40be990696b 100644
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -410,11 +410,11 @@  MiscInitialization (
   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
     //
     // The PEI phase should be exited with fully accessibe ACPI PM IO space:
     // 1. set PMBA
     //
-    PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0,
+    PciAndThenOr32 (Pmba, ~(UINT32)PIIX4_PMBA_MASK,
       FixedPcdGet16 (PcdPiix4AcpiPmBaseAddress));
 
     //
     // 2. set PCICMD/IOSE
     //