| Message ID | 1462882313-7637-5-git-send-email-ard.biesheuvel@linaro.org |
|---|---|
| State | New |
| Headers | show |
diff --git a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc index 9c623f227815..c4c1c231acfb 100644 --- a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc +++ b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc @@ -506,6 +506,8 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE + # SMBIOS 3.0 only + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 [PcdsDynamicDefault.common] gAmdStyxTokenSpaceGuid.PcdSocCoreCount|$(NUM_CORES) diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index b471ddf8616c..29d8ee239e96 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -519,6 +519,8 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) gAmdStyxTokenSpaceGuid.PcdIscpSupport|FALSE !endif + # SMBIOS 3.0 only + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 [PcdsDynamicDefault.common] gAmdStyxTokenSpaceGuid.PcdSocCoreCount|$(NUM_CORES)
The pre-v3.0 SMBIOS entry point only has a 32-bit field to store the address of the structure table, and so it does not make sense to attempt to generate such an entry point if you don't have any RAM below 4 GB. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc | 2 ++ Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 2 ++ 2 files changed, 4 insertions(+)