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[v5,01/10] ARM: armv7: add non-SPL enable for Cortex SMPEN

Message ID 20230424011515.1359255-2-ralph.siemsen@linaro.org
State Superseded
Headers show
Series Renesas RZ/N1 SoC initial support | expand

Commit Message

Ralph Siemsen April 24, 2023, 1:15 a.m. UTC 
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
This will be used by the following commit that adds RZ/N1 support.

Changes in v5:
- add R-b tag

 arch/arm/cpu/armv7/Kconfig | 5 +++++
 1 file changed, 5 insertions(+)
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Patch

diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index f1e4e26b8f..e33e53636a 100644
--- a/arch/arm/cpu/armv7/Kconfig
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -107,6 +107,11 @@  config ARMV7_LPAE
 	Say Y here to use the long descriptor page table format. This is
 	required if U-Boot runs in HYP mode.
 
+config ARMV7_SET_CORTEX_SMPEN
+	bool
+	help
+	  Enable the ARM Cortex ACTLR.SMP enable bit in U-boot.
+
 config SPL_ARMV7_SET_CORTEX_SMPEN
 	bool
 	help