diff mbox series

[v5,08/10] board: schneider: add RZN1 board support

Message ID 20230424011515.1359255-9-ralph.siemsen@linaro.org
State Superseded
Headers show
Series Renesas RZ/N1 SoC initial support | expand

Commit Message

Ralph Siemsen April 24, 2023, 1:15 a.m. UTC 
Add support for Schneider Electronics RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.

The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
---

Changes in v5:
- put all local DTS changes in r9a06g032-rzn1-snarc.dts
- move board-specific DDR init out of drivers/ram/cadence.
- tables of DDR paramters are now stored in devicetree
- support two different DDR memory types
- use BIT() macro
- obtain RZN1_DDR_BASE from DT
- uncomment error return when syscon fails
- make some functions static

Changes in v4:
- add binman support via r9a06g032-rzn1-snarc-u-boot.dtsi

Changes in v3:
- rename board LCES to rzn1-snarc
- move CONFIG_SYS_NS16550_MEM32 to Kconfig
- define CFG_SYS_INIT_RAM_{ADDR,SIZE}
- removed debug uart settings from defconfig

 arch/arm/dts/r9a06g032-ddr.dtsi               | 512 ++++++++++++++++++
 arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi |  23 +
 arch/arm/dts/r9a06g032-rzn1-snarc.dts         |  92 ++++
 board/schneider/rzn1-snarc/Kconfig            |  18 +
 board/schneider/rzn1-snarc/Makefile           |   3 +
 board/schneider/rzn1-snarc/ddr_async.c        | 377 +++++++++++++
 board/schneider/rzn1-snarc/rzn1.c             |  40 ++
 configs/rzn1_snarc_defconfig                  |  24 +
 include/configs/rzn1-snarc.h                  |  13 +
 include/renesas/is43tr16256a_125k_CTL.h       | 419 ++++++++++++++
 .../renesas/jedec_ddr3_2g_x16_1333h_500_cl8.h | 399 ++++++++++++++
 11 files changed, 1920 insertions(+)
 create mode 100644 arch/arm/dts/r9a06g032-ddr.dtsi
 create mode 100644 arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi
 create mode 100644 arch/arm/dts/r9a06g032-rzn1-snarc.dts
 create mode 100644 board/schneider/rzn1-snarc/Kconfig
 create mode 100644 board/schneider/rzn1-snarc/Makefile
 create mode 100644 board/schneider/rzn1-snarc/ddr_async.c
 create mode 100644 board/schneider/rzn1-snarc/rzn1.c
 create mode 100644 configs/rzn1_snarc_defconfig
 create mode 100644 include/configs/rzn1-snarc.h
 create mode 100644 include/renesas/is43tr16256a_125k_CTL.h
 create mode 100644 include/renesas/jedec_ddr3_2g_x16_1333h_500_cl8.h

Comments

Marek Vasut May 7, 2023, 4:06 p.m. UTC | #1 
On 4/24/23 03:15, Ralph Siemsen wrote:
> Add support for Schneider Electronics RZ/N1D and RZ/N1S boards, which
> are based on the Reneasas RZ/N1 SoC devices.
> 
> The intention is to support both boards using a single defconfig, and to
> handle the differences at runtime.

The DT comes from Linux kernel, right ? Please include commit ID from 
which the DT is imported in the commit message, I suspect that would be 
Linux 6.3 commit ID.

[...]

> diff --git a/board/schneider/rzn1-snarc/ddr_async.c b/board/schneider/rzn1-snarc/ddr_async.c
> new file mode 100644
> index 0000000000..4b4c280e45
> --- /dev/null
> +++ b/board/schneider/rzn1-snarc/ddr_async.c

Please correct me if I'm wrong, but shouldn't this be in drivers/ram/ ?

[...]

> +/* DDR PHY setup */
> +static void ddr_phy_init(struct cadence_ddr_info *priv, int ddr_type)
> +{
> +	u32 val;
> +
> +	/* Disable DDR Controller clock and FlexWAY connection */
> +	clk_disable(&priv->hclk_ddrc);
> +	clk_disable(&priv->clk_ddrc);
> +
> +	clk_rzn1_reset_state(&priv->hclk_ddrc, 0);
> +	clk_rzn1_reset_state(&priv->clk_ddrc, 0);
> +
> +	/* Enable DDR Controller clock and FlexWAY connection */
> +	clk_enable(&priv->clk_ddrc);
> +	clk_enable(&priv->hclk_ddrc);
> +
> +	/* DDR PHY Soft reset assert */
> +	ddrc_writel(FUNCCTRL_MASKSDLOFS | FUNCCTRL_DVDDQ_1_5V, FUNCCTRL);
> +
> +	clk_rzn1_reset_state(&priv->hclk_ddrc, 1);
> +	clk_rzn1_reset_state(&priv->clk_ddrc, 1);
> +
> +	/* DDR PHY setup */
> +	phy_writel(DLLCTRL_MFSL_500MHz | DLLCTRL_MDLLSTBY, DLLCTRL);
> +	phy_writel(0x00000182, ZQCALCTRL);
> +	if (ddr_type == RZN1_DDR3_DUAL_BANK)
> +		phy_writel(0xAB330031, ZQODTCTRL);
> +	else if (ddr_type == RZN1_DDR3_SINGLE_BANK)
> +		phy_writel(0xAB320051, ZQODTCTRL);
> +	else /* DDR2 */
> +		phy_writel(0xAB330071, ZQODTCTRL);
> +	phy_writel(0xB545B544, RDCTRL);
> +	phy_writel(0x000000B0, RDTMG);
> +	phy_writel(0x020A0806, OUTCTRL);
> +	if (ddr_type == RZN1_DDR3_DUAL_BANK)
> +		phy_writel(0x80005556, WLCTRL1);
> +	else
> +		phy_writel(0x80005C5D, WLCTRL1);
> +	phy_writel(0x00000101, FIFOINIT);
> +	phy_writel(0x00004545, DQCALOFS1);
> +
> +	/* Step 9 MDLL reset release */
> +	val = phy_readl(DLLCTRL);
> +	val &= ~DLLCTRL_MDLLSTBY;
> +	phy_writel(val, DLLCTRL);
> +
> +	/* Step 12 Soft reset release */
> +	val = phy_readl(FUNCCTRL);
> +	val |= FUNCCTRL_RESET_N;
> +	phy_writel(val, FUNCCTRL);
> +
> +	/* Step 13 FIFO pointer initialize */
> +	phy_writel(FIFOINIT_RDPTINITEXE | FIFOINIT_WRPTINITEXE, FIFOINIT);
> +
> +	/* Step 14 Execute ZQ Calibration */
> +	val = phy_readl(ZQCALCTRL);
> +	val |= ZQCALCTRL_ZQCALRSTB;
> +	phy_writel(val, ZQCALCTRL);
> +
> +	/* Step 15 Wait for 200us or more, or wait for DFIINITCOMPLETE to be "1" */
> +	while (!(phy_readl(DLLCTRL) & DLLCTRL_ASDLLOCK))
> +		;

Please avoid endless loops, use readl_poll_timeout() or wait_for_bit*() 
where possible.

> +	while (!(phy_readl(ZQCALCTRL) & ZQCALCTRL_ZQCALEND))
> +		;
> +
> +	/* Step 16 Enable Address and Command output */
> +	val = phy_readl(OUTCTRL);
> +	val |= OUTCTRL_ADCMDOE;
> +	phy_writel(val, OUTCTRL);
> +
> +	/* Step 17 Wait for 200us or more(from MRESETB=0) */
> +	udelay(200);
> +}

[...]

> diff --git a/board/schneider/rzn1-snarc/rzn1.c b/board/schneider/rzn1-snarc/rzn1.c
> new file mode 100644
> index 0000000000..6eb86c2592
> --- /dev/null
> +++ b/board/schneider/rzn1-snarc/rzn1.c
> @@ -0,0 +1,40 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <ram.h>
> +#include <asm/global_data.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int board_init(void)
> +{
> +	/*
> +	 * Initial values for gd->ram_base and gd->ram_size
> +	 * are obtained from the "/memory" node in devicetree.
> +	 * The size will be updated in later when probing DDR.
> +	 */
> +	fdtdec_setup_mem_size_base();

Are you absolutely sure this call ^ is needed at all ?

> +	gd->bd->bi_boot_params = gd->ram_base + 0x100;
> +
> +	return 0;
> +}
> +
> +int dram_init(void)
> +{
> +	struct udevice *dev;
> +	int err;
> +
> +	/*
> +	 * This will end up calling cadence_ddr_probe(),
> +	 * and will also update gd->ram_size.
> +	 */
> +	err = uclass_get_device(UCLASS_RAM, 0, &dev);
> +	if (err) {
> +		debug("DRAM init failed: %d\n", err);

You can just do this here:

err = uclass...();
if (err)
   debug(...);

return err;

> +		return err;
> +	}
> +
> +	return 0;
> +}

[...]

narc.h b/include/configs/rzn1-snarc.h
> new file mode 100644
> index 0000000000..dce0de0d4c
> --- /dev/null
> +++ b/include/configs/rzn1-snarc.h
> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Configuration settings for the Schneider RZ/N1 board
> + */
> +
> +#ifndef __RZN1_H

Better use __RZN1_SNARC_H , so that when other boards get added, there 
won't be trouble.

> +#define __RZN1_H
> +
> +/* Internal RAM */
> +#define CFG_SYS_INIT_RAM_ADDR	0x20000000
> +#define CFG_SYS_INIT_RAM_SIZE	(1 * 1024 * 1024)
> +
> +#endif	/* __RZN1_H */
Ralph Siemsen May 8, 2023, 6:23 p.m. UTC | #2 
On Sun, May 07, 2023 at 06:06:40PM +0200, Marek Vasut wrote:
>On 4/24/23 03:15, Ralph Siemsen wrote:
>>Add support for Schneider Electronics RZ/N1D and RZ/N1S boards, which
>>are based on the Reneasas RZ/N1 SoC devices.
>>
>>The intention is to support both boards using a single defconfig, and to
>>handle the differences at runtime.
>
>The DT comes from Linux kernel, right ? Please include commit ID from 
>which the DT is imported in the commit message, I suspect that would 
>be Linux 6.3 commit ID.

Yes, the DT is copied verbatim from Linux. I have updated the commit 
message to mention 6.3 and include the hash. (There have been no changes 

>
>>diff --git a/board/schneider/rzn1-snarc/ddr_async.c b/board/schneider/rzn1-snarc/ddr_async.c
>>new file mode 100644
>>index 0000000000..4b4c280e45
>>--- /dev/null
>>+++ b/board/schneider/rzn1-snarc/ddr_async.c
>
>Please correct me if I'm wrong, but shouldn't this be in drivers/ram/ ?

I had it there originally, but moved it in v5 of the patch series. There 
is a lot of board-specific (or at least architecture-specific) logic in 
this file. For example the sequence of steps to setup the clocks and 
interconnect, prior to bringing the DDR controller out of reset. This 
depends on choices made by the RZ/N1 designers, rather than the CDNS IP 
that drivers/ram/cadence is aiming to cover.

Likewise for some board-specific PHY settings, and choices such as 
operating in async mode.

I moved it to board-specific directory as an interim step. Hopefully we 
can do some consolidation of the multiple CDNS DDR controller 
implementations, and then figure out the right way to split things up.

For now this seemed like the less-bad option.

>>+
>>+	/* Step 15 Wait for 200us or more, or wait for DFIINITCOMPLETE to be "1" */
>>+	while (!(phy_readl(DLLCTRL) & DLLCTRL_ASDLLOCK))
>>+		;
>
>Please avoid endless loops, use readl_poll_timeout() or 
>wait_for_bit*() where possible.

Will do.

>>+int board_init(void)
>>+{
>>+	/*
>>+	 * Initial values for gd->ram_base and gd->ram_size
>>+	 * are obtained from the "/memory" node in devicetree.
>>+	 * The size will be updated in later when probing DDR.
>>+	 */
>>+	fdtdec_setup_mem_size_base();
>
>Are you absolutely sure this call ^ is needed at all ?

I was sure at the time when I wrote it, however I just tried removing it 
now and it seems to work fine.

>You can just do this here:
>
>err = uclass...();
>if (err)
>  debug(...);
>
>return err;

Done.

>>+#ifndef __RZN1_H
>
>Better use __RZN1_SNARC_H , so that when other boards get added, there 
>won't be trouble.

Good catch, done.

Ralph
Marek Vasut May 9, 2023, 2:26 a.m. UTC | #3 
On 5/8/23 20:23, Ralph Siemsen wrote:
> On Sun, May 07, 2023 at 06:06:40PM +0200, Marek Vasut wrote:
>> On 4/24/23 03:15, Ralph Siemsen wrote:
>>> Add support for Schneider Electronics RZ/N1D and RZ/N1S boards, which
>>> are based on the Reneasas RZ/N1 SoC devices.
>>>
>>> The intention is to support both boards using a single defconfig, and to
>>> handle the differences at runtime.
>>
>> The DT comes from Linux kernel, right ? Please include commit ID from 
>> which the DT is imported in the commit message, I suspect that would 
>> be Linux 6.3 commit ID.
> 
> Yes, the DT is copied verbatim from Linux. I have updated the commit 
> message to mention 6.3 and include the hash. (There have been no changes

Thanks

>>> diff --git a/board/schneider/rzn1-snarc/ddr_async.c 
>>> b/board/schneider/rzn1-snarc/ddr_async.c
>>> new file mode 100644
>>> index 0000000000..4b4c280e45
>>> --- /dev/null
>>> +++ b/board/schneider/rzn1-snarc/ddr_async.c
>>
>> Please correct me if I'm wrong, but shouldn't this be in drivers/ram/ ?
> 
> I had it there originally, but moved it in v5 of the patch series. There 
> is a lot of board-specific (or at least architecture-specific) logic in 
> this file. For example the sequence of steps to setup the clocks and 
> interconnect, prior to bringing the DDR controller out of reset. This 
> depends on choices made by the RZ/N1 designers, rather than the CDNS IP 
> that drivers/ram/cadence is aiming to cover.
> 
> Likewise for some board-specific PHY settings, and choices such as 
> operating in async mode.
> 
> I moved it to board-specific directory as an interim step. Hopefully we 
> can do some consolidation of the multiple CDNS DDR controller 
> implementations, and then figure out the right way to split things up.
> 
> For now this seemed like the less-bad option.

How about putting it into drivers/soc/ ?
Ralph Siemsen May 9, 2023, 1:21 p.m. UTC | #4 
On Tue, May 09, 2023 at 04:26:57AM +0200, Marek Vasut wrote:
>On 5/8/23 20:23, Ralph Siemsen wrote:
>>I moved it to board-specific directory as an interim step. Hopefully 
>>we can do some consolidation of the multiple CDNS DDR controller 
>>implementations, and then figure out the right way to split things up.
>>
>>For now this seemed like the less-bad option.
>
>How about putting it into drivers/soc/ ?

Possibly, although it would complicate things for me right now. I have 
some (as yet unfinished) patches to handle the RZ/N1 variants using 
drivers/soc.

Ralph
Ralph Siemsen May 12, 2023, 8:12 p.m. UTC | #5 
On Tue, May 09, 2023 at 09:21:02AM -0400, Ralph Siemsen wrote:
>On Tue, May 09, 2023 at 04:26:57AM +0200, Marek Vasut wrote:
>>On 5/8/23 20:23, Ralph Siemsen wrote:
>>>I moved it to board-specific directory as an interim step. 
>>>Hopefully we can do some consolidation of the multiple CDNS DDR 
>>>controller implementations, and then figure out the right way to 
>>>split things up.
>>>
>>>For now this seemed like the less-bad option.
>>
>>How about putting it into drivers/soc/ ?
>
>Possibly, although it would complicate things for me right now. I have 
>some (as yet unfinished) patches to handle the RZ/N1 variants using 
>drivers/soc.

As discussed on IRC, it is now moved into drivers/ram/renesas/rzn1

Ralph
diff mbox series

Patch

diff --git a/arch/arm/dts/r9a06g032-ddr.dtsi b/arch/arm/dts/r9a06g032-ddr.dtsi
new file mode 100644
index 0000000000..8c7d0873fe
--- /dev/null
+++ b/arch/arm/dts/r9a06g032-ddr.dtsi
@@ -0,0 +1,512 @@ 
+// SPDX-License-Identifier: GPL-2.0
+
+	cadence,ctl-000 = <
+		DENALI_CTL_00_DATA
+		DENALI_CTL_01_DATA
+		DENALI_CTL_02_DATA
+		DENALI_CTL_03_DATA
+		DENALI_CTL_04_DATA
+		DENALI_CTL_05_DATA
+		DENALI_CTL_06_DATA
+		DENALI_CTL_07_DATA
+		DENALI_CTL_08_DATA
+		DENALI_CTL_09_DATA
+
+		DENALI_CTL_10_DATA
+		DENALI_CTL_11_DATA
+		DENALI_CTL_12_DATA
+		DENALI_CTL_13_DATA
+		DENALI_CTL_14_DATA
+		DENALI_CTL_15_DATA
+		DENALI_CTL_16_DATA
+		DENALI_CTL_17_DATA
+		DENALI_CTL_18_DATA
+		DENALI_CTL_19_DATA
+
+		DENALI_CTL_20_DATA
+		DENALI_CTL_21_DATA
+		DENALI_CTL_22_DATA
+		DENALI_CTL_23_DATA
+		DENALI_CTL_24_DATA
+		DENALI_CTL_25_DATA
+		DENALI_CTL_26_DATA
+		DENALI_CTL_27_DATA
+		DENALI_CTL_28_DATA
+		DENALI_CTL_29_DATA
+
+		DENALI_CTL_30_DATA
+		DENALI_CTL_31_DATA
+		DENALI_CTL_32_DATA
+		DENALI_CTL_33_DATA
+		DENALI_CTL_34_DATA
+		DENALI_CTL_35_DATA
+		DENALI_CTL_36_DATA
+		DENALI_CTL_37_DATA
+		DENALI_CTL_38_DATA
+		DENALI_CTL_39_DATA
+
+		DENALI_CTL_40_DATA
+		DENALI_CTL_41_DATA
+		DENALI_CTL_42_DATA
+		DENALI_CTL_43_DATA
+		DENALI_CTL_44_DATA
+		DENALI_CTL_45_DATA
+		DENALI_CTL_46_DATA
+		DENALI_CTL_47_DATA
+		DENALI_CTL_48_DATA
+		DENALI_CTL_49_DATA
+
+		DENALI_CTL_50_DATA
+		DENALI_CTL_51_DATA
+		DENALI_CTL_52_DATA
+		DENALI_CTL_53_DATA
+		DENALI_CTL_54_DATA
+		DENALI_CTL_55_DATA
+		DENALI_CTL_56_DATA
+		DENALI_CTL_57_DATA
+		DENALI_CTL_58_DATA
+		DENALI_CTL_59_DATA
+
+		DENALI_CTL_60_DATA
+		DENALI_CTL_61_DATA
+		DENALI_CTL_62_DATA
+		DENALI_CTL_63_DATA
+		DENALI_CTL_64_DATA
+		DENALI_CTL_65_DATA
+		DENALI_CTL_66_DATA
+		DENALI_CTL_67_DATA
+		DENALI_CTL_68_DATA
+		DENALI_CTL_69_DATA
+
+		DENALI_CTL_70_DATA
+		DENALI_CTL_71_DATA
+		DENALI_CTL_72_DATA
+		DENALI_CTL_73_DATA
+		DENALI_CTL_74_DATA
+		DENALI_CTL_75_DATA
+		DENALI_CTL_76_DATA
+		DENALI_CTL_77_DATA
+		DENALI_CTL_78_DATA
+		DENALI_CTL_79_DATA
+
+		DENALI_CTL_80_DATA
+		DENALI_CTL_81_DATA
+		DENALI_CTL_82_DATA
+		DENALI_CTL_83_DATA
+		DENALI_CTL_84_DATA
+		DENALI_CTL_85_DATA
+		DENALI_CTL_86_DATA
+		DENALI_CTL_87_DATA
+		DENALI_CTL_88_DATA
+		DENALI_CTL_89_DATA
+
+		DENALI_CTL_90_DATA
+		DENALI_CTL_91_DATA
+		DENALI_CTL_92_DATA
+	>;
+
+	cadence,ctl-350 = <
+		DENALI_CTL_350_DATA
+		DENALI_CTL_351_DATA
+		DENALI_CTL_352_DATA
+		DENALI_CTL_353_DATA
+		DENALI_CTL_354_DATA
+		DENALI_CTL_355_DATA
+		DENALI_CTL_356_DATA
+		DENALI_CTL_357_DATA
+		DENALI_CTL_358_DATA
+		DENALI_CTL_359_DATA
+
+		DENALI_CTL_360_DATA
+		DENALI_CTL_361_DATA
+		DENALI_CTL_362_DATA
+		DENALI_CTL_363_DATA
+		DENALI_CTL_364_DATA
+		DENALI_CTL_365_DATA
+		DENALI_CTL_366_DATA
+		DENALI_CTL_367_DATA
+		DENALI_CTL_368_DATA
+		DENALI_CTL_369_DATA
+
+		DENALI_CTL_370_DATA
+		DENALI_CTL_371_DATA
+		DENALI_CTL_372_DATA
+		DENALI_CTL_373_DATA
+		DENALI_CTL_374_DATA
+	>;
+
+#undef DENALI_CTL_00_DATA
+#undef DENALI_CTL_01_DATA
+#undef DENALI_CTL_02_DATA
+#undef DENALI_CTL_03_DATA
+#undef DENALI_CTL_04_DATA
+#undef DENALI_CTL_05_DATA
+#undef DENALI_CTL_06_DATA
+#undef DENALI_CTL_07_DATA
+#undef DENALI_CTL_08_DATA
+#undef DENALI_CTL_09_DATA
+#undef DENALI_CTL_10_DATA
+#undef DENALI_CTL_11_DATA
+#undef DENALI_CTL_12_DATA
+#undef DENALI_CTL_13_DATA
+#undef DENALI_CTL_14_DATA
+#undef DENALI_CTL_15_DATA
+#undef DENALI_CTL_16_DATA
+#undef DENALI_CTL_17_DATA
+#undef DENALI_CTL_18_DATA
+#undef DENALI_CTL_19_DATA
+#undef DENALI_CTL_20_DATA
+#undef DENALI_CTL_21_DATA
+#undef DENALI_CTL_22_DATA
+#undef DENALI_CTL_23_DATA
+#undef DENALI_CTL_24_DATA
+#undef DENALI_CTL_25_DATA
+#undef DENALI_CTL_26_DATA
+#undef DENALI_CTL_27_DATA
+#undef DENALI_CTL_28_DATA
+#undef DENALI_CTL_29_DATA
+#undef DENALI_CTL_30_DATA
+#undef DENALI_CTL_31_DATA
+#undef DENALI_CTL_32_DATA
+#undef DENALI_CTL_33_DATA
+#undef DENALI_CTL_34_DATA
+#undef DENALI_CTL_35_DATA
+#undef DENALI_CTL_36_DATA
+#undef DENALI_CTL_37_DATA
+#undef DENALI_CTL_38_DATA
+#undef DENALI_CTL_39_DATA
+#undef DENALI_CTL_40_DATA
+#undef DENALI_CTL_41_DATA
+#undef DENALI_CTL_42_DATA
+#undef DENALI_CTL_43_DATA
+#undef DENALI_CTL_44_DATA
+#undef DENALI_CTL_45_DATA
+#undef DENALI_CTL_46_DATA
+#undef DENALI_CTL_47_DATA
+#undef DENALI_CTL_48_DATA
+#undef DENALI_CTL_49_DATA
+#undef DENALI_CTL_50_DATA
+#undef DENALI_CTL_51_DATA
+#undef DENALI_CTL_52_DATA
+#undef DENALI_CTL_53_DATA
+#undef DENALI_CTL_54_DATA
+#undef DENALI_CTL_55_DATA
+#undef DENALI_CTL_56_DATA
+#undef DENALI_CTL_57_DATA
+#undef DENALI_CTL_58_DATA
+#undef DENALI_CTL_59_DATA
+#undef DENALI_CTL_60_DATA
+#undef DENALI_CTL_61_DATA
+#undef DENALI_CTL_62_DATA
+#undef DENALI_CTL_63_DATA
+#undef DENALI_CTL_64_DATA
+#undef DENALI_CTL_65_DATA
+#undef DENALI_CTL_66_DATA
+#undef DENALI_CTL_67_DATA
+#undef DENALI_CTL_68_DATA
+#undef DENALI_CTL_69_DATA
+#undef DENALI_CTL_70_DATA
+#undef DENALI_CTL_71_DATA
+#undef DENALI_CTL_72_DATA
+#undef DENALI_CTL_73_DATA
+#undef DENALI_CTL_74_DATA
+#undef DENALI_CTL_75_DATA
+#undef DENALI_CTL_76_DATA
+#undef DENALI_CTL_77_DATA
+#undef DENALI_CTL_78_DATA
+#undef DENALI_CTL_79_DATA
+#undef DENALI_CTL_80_DATA
+#undef DENALI_CTL_81_DATA
+#undef DENALI_CTL_82_DATA
+#undef DENALI_CTL_83_DATA
+#undef DENALI_CTL_84_DATA
+#undef DENALI_CTL_85_DATA
+#undef DENALI_CTL_86_DATA
+#undef DENALI_CTL_87_DATA
+#undef DENALI_CTL_88_DATA
+#undef DENALI_CTL_89_DATA
+#undef DENALI_CTL_90_DATA
+#undef DENALI_CTL_91_DATA
+#undef DENALI_CTL_92_DATA
+#undef DENALI_CTL_93_DATA
+#undef DENALI_CTL_94_DATA
+#undef DENALI_CTL_95_DATA
+#undef DENALI_CTL_96_DATA
+#undef DENALI_CTL_97_DATA
+#undef DENALI_CTL_98_DATA
+#undef DENALI_CTL_99_DATA
+#undef DENALI_CTL_100_DATA
+#undef DENALI_CTL_101_DATA
+#undef DENALI_CTL_102_DATA
+#undef DENALI_CTL_103_DATA
+#undef DENALI_CTL_104_DATA
+#undef DENALI_CTL_105_DATA
+#undef DENALI_CTL_106_DATA
+#undef DENALI_CTL_107_DATA
+#undef DENALI_CTL_108_DATA
+#undef DENALI_CTL_109_DATA
+#undef DENALI_CTL_110_DATA
+#undef DENALI_CTL_111_DATA
+#undef DENALI_CTL_112_DATA
+#undef DENALI_CTL_113_DATA
+#undef DENALI_CTL_114_DATA
+#undef DENALI_CTL_115_DATA
+#undef DENALI_CTL_116_DATA
+#undef DENALI_CTL_117_DATA
+#undef DENALI_CTL_118_DATA
+#undef DENALI_CTL_119_DATA
+#undef DENALI_CTL_120_DATA
+#undef DENALI_CTL_121_DATA
+#undef DENALI_CTL_122_DATA
+#undef DENALI_CTL_123_DATA
+#undef DENALI_CTL_124_DATA
+#undef DENALI_CTL_125_DATA
+#undef DENALI_CTL_126_DATA
+#undef DENALI_CTL_127_DATA
+#undef DENALI_CTL_128_DATA
+#undef DENALI_CTL_129_DATA
+#undef DENALI_CTL_130_DATA
+#undef DENALI_CTL_131_DATA
+#undef DENALI_CTL_132_DATA
+#undef DENALI_CTL_133_DATA
+#undef DENALI_CTL_134_DATA
+#undef DENALI_CTL_135_DATA
+#undef DENALI_CTL_136_DATA
+#undef DENALI_CTL_137_DATA
+#undef DENALI_CTL_138_DATA
+#undef DENALI_CTL_139_DATA
+#undef DENALI_CTL_140_DATA
+#undef DENALI_CTL_141_DATA
+#undef DENALI_CTL_142_DATA
+#undef DENALI_CTL_143_DATA
+#undef DENALI_CTL_144_DATA
+#undef DENALI_CTL_145_DATA
+#undef DENALI_CTL_146_DATA
+#undef DENALI_CTL_147_DATA
+#undef DENALI_CTL_148_DATA
+#undef DENALI_CTL_149_DATA
+#undef DENALI_CTL_150_DATA
+#undef DENALI_CTL_151_DATA
+#undef DENALI_CTL_152_DATA
+#undef DENALI_CTL_153_DATA
+#undef DENALI_CTL_154_DATA
+#undef DENALI_CTL_155_DATA
+#undef DENALI_CTL_156_DATA
+#undef DENALI_CTL_157_DATA
+#undef DENALI_CTL_158_DATA
+#undef DENALI_CTL_159_DATA
+#undef DENALI_CTL_160_DATA
+#undef DENALI_CTL_161_DATA
+#undef DENALI_CTL_162_DATA
+#undef DENALI_CTL_163_DATA
+#undef DENALI_CTL_164_DATA
+#undef DENALI_CTL_165_DATA
+#undef DENALI_CTL_166_DATA
+#undef DENALI_CTL_167_DATA
+#undef DENALI_CTL_168_DATA
+#undef DENALI_CTL_169_DATA
+#undef DENALI_CTL_170_DATA
+#undef DENALI_CTL_171_DATA
+#undef DENALI_CTL_172_DATA
+#undef DENALI_CTL_173_DATA
+#undef DENALI_CTL_174_DATA
+#undef DENALI_CTL_175_DATA
+#undef DENALI_CTL_176_DATA
+#undef DENALI_CTL_177_DATA
+#undef DENALI_CTL_178_DATA
+#undef DENALI_CTL_179_DATA
+#undef DENALI_CTL_180_DATA
+#undef DENALI_CTL_181_DATA
+#undef DENALI_CTL_182_DATA
+#undef DENALI_CTL_183_DATA
+#undef DENALI_CTL_184_DATA
+#undef DENALI_CTL_185_DATA
+#undef DENALI_CTL_186_DATA
+#undef DENALI_CTL_187_DATA
+#undef DENALI_CTL_188_DATA
+#undef DENALI_CTL_189_DATA
+#undef DENALI_CTL_190_DATA
+#undef DENALI_CTL_191_DATA
+#undef DENALI_CTL_192_DATA
+#undef DENALI_CTL_193_DATA
+#undef DENALI_CTL_194_DATA
+#undef DENALI_CTL_195_DATA
+#undef DENALI_CTL_196_DATA
+#undef DENALI_CTL_197_DATA
+#undef DENALI_CTL_198_DATA
+#undef DENALI_CTL_199_DATA
+#undef DENALI_CTL_200_DATA
+#undef DENALI_CTL_201_DATA
+#undef DENALI_CTL_202_DATA
+#undef DENALI_CTL_203_DATA
+#undef DENALI_CTL_204_DATA
+#undef DENALI_CTL_205_DATA
+#undef DENALI_CTL_206_DATA
+#undef DENALI_CTL_207_DATA
+#undef DENALI_CTL_208_DATA
+#undef DENALI_CTL_209_DATA
+#undef DENALI_CTL_210_DATA
+#undef DENALI_CTL_211_DATA
+#undef DENALI_CTL_212_DATA
+#undef DENALI_CTL_213_DATA
+#undef DENALI_CTL_214_DATA
+#undef DENALI_CTL_215_DATA
+#undef DENALI_CTL_216_DATA
+#undef DENALI_CTL_217_DATA
+#undef DENALI_CTL_218_DATA
+#undef DENALI_CTL_219_DATA
+#undef DENALI_CTL_220_DATA
+#undef DENALI_CTL_221_DATA
+#undef DENALI_CTL_222_DATA
+#undef DENALI_CTL_223_DATA
+#undef DENALI_CTL_224_DATA
+#undef DENALI_CTL_225_DATA
+#undef DENALI_CTL_226_DATA
+#undef DENALI_CTL_227_DATA
+#undef DENALI_CTL_228_DATA
+#undef DENALI_CTL_229_DATA
+#undef DENALI_CTL_230_DATA
+#undef DENALI_CTL_231_DATA
+#undef DENALI_CTL_232_DATA
+#undef DENALI_CTL_233_DATA
+#undef DENALI_CTL_234_DATA
+#undef DENALI_CTL_235_DATA
+#undef DENALI_CTL_236_DATA
+#undef DENALI_CTL_237_DATA
+#undef DENALI_CTL_238_DATA
+#undef DENALI_CTL_239_DATA
+#undef DENALI_CTL_240_DATA
+#undef DENALI_CTL_241_DATA
+#undef DENALI_CTL_242_DATA
+#undef DENALI_CTL_243_DATA
+#undef DENALI_CTL_244_DATA
+#undef DENALI_CTL_245_DATA
+#undef DENALI_CTL_246_DATA
+#undef DENALI_CTL_247_DATA
+#undef DENALI_CTL_248_DATA
+#undef DENALI_CTL_249_DATA
+#undef DENALI_CTL_250_DATA
+#undef DENALI_CTL_251_DATA
+#undef DENALI_CTL_252_DATA
+#undef DENALI_CTL_253_DATA
+#undef DENALI_CTL_254_DATA
+#undef DENALI_CTL_255_DATA
+#undef DENALI_CTL_256_DATA
+#undef DENALI_CTL_257_DATA
+#undef DENALI_CTL_258_DATA
+#undef DENALI_CTL_259_DATA
+#undef DENALI_CTL_260_DATA
+#undef DENALI_CTL_261_DATA
+#undef DENALI_CTL_262_DATA
+#undef DENALI_CTL_263_DATA
+#undef DENALI_CTL_264_DATA
+#undef DENALI_CTL_265_DATA
+#undef DENALI_CTL_266_DATA
+#undef DENALI_CTL_267_DATA
+#undef DENALI_CTL_268_DATA
+#undef DENALI_CTL_269_DATA
+#undef DENALI_CTL_270_DATA
+#undef DENALI_CTL_271_DATA
+#undef DENALI_CTL_272_DATA
+#undef DENALI_CTL_273_DATA
+#undef DENALI_CTL_274_DATA
+#undef DENALI_CTL_275_DATA
+#undef DENALI_CTL_276_DATA
+#undef DENALI_CTL_277_DATA
+#undef DENALI_CTL_278_DATA
+#undef DENALI_CTL_279_DATA
+#undef DENALI_CTL_280_DATA
+#undef DENALI_CTL_281_DATA
+#undef DENALI_CTL_282_DATA
+#undef DENALI_CTL_283_DATA
+#undef DENALI_CTL_284_DATA
+#undef DENALI_CTL_285_DATA
+#undef DENALI_CTL_286_DATA
+#undef DENALI_CTL_287_DATA
+#undef DENALI_CTL_288_DATA
+#undef DENALI_CTL_289_DATA
+#undef DENALI_CTL_290_DATA
+#undef DENALI_CTL_291_DATA
+#undef DENALI_CTL_292_DATA
+#undef DENALI_CTL_293_DATA
+#undef DENALI_CTL_294_DATA
+#undef DENALI_CTL_295_DATA
+#undef DENALI_CTL_296_DATA
+#undef DENALI_CTL_297_DATA
+#undef DENALI_CTL_298_DATA
+#undef DENALI_CTL_299_DATA
+#undef DENALI_CTL_300_DATA
+#undef DENALI_CTL_301_DATA
+#undef DENALI_CTL_302_DATA
+#undef DENALI_CTL_303_DATA
+#undef DENALI_CTL_304_DATA
+#undef DENALI_CTL_305_DATA
+#undef DENALI_CTL_306_DATA
+#undef DENALI_CTL_307_DATA
+#undef DENALI_CTL_308_DATA
+#undef DENALI_CTL_309_DATA
+#undef DENALI_CTL_310_DATA
+#undef DENALI_CTL_311_DATA
+#undef DENALI_CTL_312_DATA
+#undef DENALI_CTL_313_DATA
+#undef DENALI_CTL_314_DATA
+#undef DENALI_CTL_315_DATA
+#undef DENALI_CTL_316_DATA
+#undef DENALI_CTL_317_DATA
+#undef DENALI_CTL_318_DATA
+#undef DENALI_CTL_319_DATA
+#undef DENALI_CTL_320_DATA
+#undef DENALI_CTL_321_DATA
+#undef DENALI_CTL_322_DATA
+#undef DENALI_CTL_323_DATA
+#undef DENALI_CTL_324_DATA
+#undef DENALI_CTL_325_DATA
+#undef DENALI_CTL_326_DATA
+#undef DENALI_CTL_327_DATA
+#undef DENALI_CTL_328_DATA
+#undef DENALI_CTL_329_DATA
+#undef DENALI_CTL_330_DATA
+#undef DENALI_CTL_331_DATA
+#undef DENALI_CTL_332_DATA
+#undef DENALI_CTL_333_DATA
+#undef DENALI_CTL_334_DATA
+#undef DENALI_CTL_335_DATA
+#undef DENALI_CTL_336_DATA
+#undef DENALI_CTL_337_DATA
+#undef DENALI_CTL_338_DATA
+#undef DENALI_CTL_339_DATA
+#undef DENALI_CTL_340_DATA
+#undef DENALI_CTL_341_DATA
+#undef DENALI_CTL_342_DATA
+#undef DENALI_CTL_343_DATA
+#undef DENALI_CTL_344_DATA
+#undef DENALI_CTL_345_DATA
+#undef DENALI_CTL_346_DATA
+#undef DENALI_CTL_347_DATA
+#undef DENALI_CTL_348_DATA
+#undef DENALI_CTL_349_DATA
+#undef DENALI_CTL_350_DATA
+#undef DENALI_CTL_351_DATA
+#undef DENALI_CTL_352_DATA
+#undef DENALI_CTL_353_DATA
+#undef DENALI_CTL_354_DATA
+#undef DENALI_CTL_355_DATA
+#undef DENALI_CTL_356_DATA
+#undef DENALI_CTL_357_DATA
+#undef DENALI_CTL_358_DATA
+#undef DENALI_CTL_359_DATA
+#undef DENALI_CTL_360_DATA
+#undef DENALI_CTL_361_DATA
+#undef DENALI_CTL_362_DATA
+#undef DENALI_CTL_363_DATA
+#undef DENALI_CTL_364_DATA
+#undef DENALI_CTL_365_DATA
+#undef DENALI_CTL_366_DATA
+#undef DENALI_CTL_367_DATA
+#undef DENALI_CTL_368_DATA
+#undef DENALI_CTL_369_DATA
+#undef DENALI_CTL_370_DATA
+#undef DENALI_CTL_371_DATA
+#undef DENALI_CTL_372_DATA
+#undef DENALI_CTL_373_DATA
+#undef DENALI_CTL_374_DATA
diff --git a/arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi b/arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi
new file mode 100644
index 0000000000..794e711103
--- /dev/null
+++ b/arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi
@@ -0,0 +1,23 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Configuration file for binman
+ *
+ * After building u-boot, can generate the SPKG output by running:
+ * tools/binman/binman build -d arch/arm/dts/r9a06g032-rzn1-snarc.dtb -O <outdir>
+ */
+
+#include <config.h>
+
+/ {
+	binman: binman {
+	};
+};
+
+&binman {
+	mkimage {
+		filename = "u-boot.bin.spkg";
+		args = "-n board/schneider/rzn1-snarc/spkgimage.cfg -T spkgimage -a 0x20040000 -e 0x20040000";
+		u-boot {
+		};
+	};
+};
diff --git a/arch/arm/dts/r9a06g032-rzn1-snarc.dts b/arch/arm/dts/r9a06g032-rzn1-snarc.dts
new file mode 100644
index 0000000000..7de8ee15ef
--- /dev/null
+++ b/arch/arm/dts/r9a06g032-rzn1-snarc.dts
@@ -0,0 +1,92 @@ 
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for Schneider RZ/N1 Board
+ *
+ * Based on r9a06g032-rzn1d400-db.dts
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/pinctrl/rzn1-pinctrl.h>
+#include "r9a06g032.dtsi"
+
+/ {
+	model = "Schneider RZ/N1 Board";
+	compatible = "schneider,rzn1", "renesas,r9a06g032";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>;
+	};
+
+	soc {
+		plat_regs: syscon@4000c000 {
+			compatible = "syscon";
+			reg = <0x4000c000 0x1000>;
+		};
+
+		system-controller@4000c000 {
+			regmap = <&plat_regs>;
+		};
+
+		ddrctrl: memory-controller@4000d000 {
+			compatible = "cadence,ddr-ctrl";
+			reg = <0x4000d000 0x1000>, <0x4000e000 0x100>;
+			reg-names = "ddrc", "phy";
+			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysctrl R9A06G032_CLK_DDRC>, <&sysctrl R9A06G032_HCLK_DDRC>;
+			clock-names = "clk_ddrc", "hclk_ddrc";
+			syscon = <&plat_regs>;
+			status = "disabled";
+		};
+	};
+
+	reboot {
+		compatible = "syscon-reboot";
+		regmap = <&plat_regs>;
+		offset = <0x198>;       /* sysctrl.RSTEN */
+		mask = <0x40>;          /* bit 6 = SWRST_REQ */
+		value = <0x40>;
+	};
+};
+
+&ddrctrl {
+	status = "okay";
+
+	conf-1 {
+		size = <0x40000000>;	/* 1 GB */
+		#include "renesas/is43tr16256a_125k_CTL.h"
+		#include "r9a06g032-ddr.dtsi"
+	};
+	conf-2 {
+		size = <0x10000000>;	/* 256 MB */
+		#include "renesas/jedec_ddr3_2g_x16_1333h_500_cl8.h"
+		#include "r9a06g032-ddr.dtsi"
+	};
+};
+
+&pinctrl {
+	status = "okay";
+
+	pins_uart0: pins_uart0 {
+		pinmux = <
+			RZN1_PINMUX(103, RZN1_FUNC_UART0_I)     /* UART0_TXD */
+			RZN1_PINMUX(104, RZN1_FUNC_UART0_I)     /* UART0_RXD */
+			>;
+		bias-disable;
+	};
+};
+
+&uart0 {
+	pinctrl-0 = <&pins_uart0>;
+	pinctrl-names = "default";
+	status = "okay";
+};
diff --git a/board/schneider/rzn1-snarc/Kconfig b/board/schneider/rzn1-snarc/Kconfig
new file mode 100644
index 0000000000..1c1c235f00
--- /dev/null
+++ b/board/schneider/rzn1-snarc/Kconfig
@@ -0,0 +1,18 @@ 
+if TARGET_SCHNEIDER_RZN1
+
+config TEXT_BASE
+	default 0x20040000
+
+config SYS_MONITOR_LEN
+	default 524288
+
+config SYS_BOARD
+	default "rzn1-snarc"
+
+config SYS_VENDOR
+	default "schneider"
+
+config SYS_CONFIG_NAME
+	default "rzn1-snarc"
+
+endif
diff --git a/board/schneider/rzn1-snarc/Makefile b/board/schneider/rzn1-snarc/Makefile
new file mode 100644
index 0000000000..c64f0f546b
--- /dev/null
+++ b/board/schneider/rzn1-snarc/Makefile
@@ -0,0 +1,3 @@ 
+# SPDX-License-Identifier:	GPL-2.0+
+
+obj-y	:= rzn1.o ddr_async.o
diff --git a/board/schneider/rzn1-snarc/ddr_async.c b/board/schneider/rzn1-snarc/ddr_async.c
new file mode 100644
index 0000000000..4b4c280e45
--- /dev/null
+++ b/board/schneider/rzn1-snarc/ddr_async.c
@@ -0,0 +1,377 @@ 
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * RZ/N1 DDR Controller initialisation
+ *
+ * The DDR Controller register values for a specific DDR device, mode and
+ * frequency are generated using a Cadence tool.
+ *
+ * Copyright (C) 2015 Renesas Electronics Europe Ltd
+ */
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <ram.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+#include <renesas/ddr_ctrl.h>
+
+void clk_rzn1_reset_state(struct clk *clk, int on);
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct cadence_ddr_info {
+	struct udevice *dev;
+	void __iomem *ddrc;
+	void __iomem *phy;
+	struct clk clk_ddrc;
+	struct clk hclk_ddrc;
+	struct regmap *syscon;
+	bool enable_ecc;
+	bool enable_8bit;
+	u32 ddr_size;
+
+	/* These two used only during .probe */
+	u32 *reg0;
+	u32 *reg350;
+};
+
+static inline u32 cadence_readl(void __iomem *addr, unsigned int offset)
+{
+	return readl(addr + offset);
+}
+
+static inline void cadence_writel(void __iomem *addr, unsigned int offset,
+				  u32 data)
+{
+	debug("%s: addr = 0x%p, value = 0x%08x\n", __func__, addr + offset, data);
+	writel(data, addr + offset);
+}
+
+#define ddrc_readl(off)		cadence_readl(priv->ddrc, off)
+#define ddrc_writel(val, off)	cadence_writel(priv->ddrc, off, val)
+
+#define phy_readl(off)		cadence_readl(priv->phy, off)
+#define phy_writel(val, off)	cadence_writel(priv->phy, off, val)
+
+#define RZN1_DDR3_SINGLE_BANK 3
+#define RZN1_DDR3_DUAL_BANK 32
+
+#define FUNCCTRL	0x00
+#define  FUNCCTRL_MASKSDLOFS	(0x18 << 16)
+#define  FUNCCTRL_DVDDQ_1_5V	BIT(8)
+#define  FUNCCTRL_RESET_N	BIT(0)
+#define DLLCTRL		0x04
+#define  DLLCTRL_ASDLLOCK	BIT(26)
+#define  DLLCTRL_MFSL_500MHz	(2 << 1)
+#define  DLLCTRL_MDLLSTBY	BIT(0)
+#define ZQCALCTRL	0x08
+#define  ZQCALCTRL_ZQCALEND	BIT(30)
+#define  ZQCALCTRL_ZQCALRSTB	BIT(0)
+#define ZQODTCTRL	0x0c
+#define RDCTRL		0x10
+#define RDTMG		0x14
+#define FIFOINIT	0x18
+#define  FIFOINIT_RDPTINITEXE	BIT(8)
+#define  FIFOINIT_WRPTINITEXE	BIT(0)
+#define OUTCTRL		0x1c
+#define  OUTCTRL_ADCMDOE	BIT(0)
+#define WLCTRL1		0x40
+#define  WLCTRL1_WLSTR		BIT(24)
+#define DQCALOFS1	0xe8
+
+/* DDR PHY setup */
+static void ddr_phy_init(struct cadence_ddr_info *priv, int ddr_type)
+{
+	u32 val;
+
+	/* Disable DDR Controller clock and FlexWAY connection */
+	clk_disable(&priv->hclk_ddrc);
+	clk_disable(&priv->clk_ddrc);
+
+	clk_rzn1_reset_state(&priv->hclk_ddrc, 0);
+	clk_rzn1_reset_state(&priv->clk_ddrc, 0);
+
+	/* Enable DDR Controller clock and FlexWAY connection */
+	clk_enable(&priv->clk_ddrc);
+	clk_enable(&priv->hclk_ddrc);
+
+	/* DDR PHY Soft reset assert */
+	ddrc_writel(FUNCCTRL_MASKSDLOFS | FUNCCTRL_DVDDQ_1_5V, FUNCCTRL);
+
+	clk_rzn1_reset_state(&priv->hclk_ddrc, 1);
+	clk_rzn1_reset_state(&priv->clk_ddrc, 1);
+
+	/* DDR PHY setup */
+	phy_writel(DLLCTRL_MFSL_500MHz | DLLCTRL_MDLLSTBY, DLLCTRL);
+	phy_writel(0x00000182, ZQCALCTRL);
+	if (ddr_type == RZN1_DDR3_DUAL_BANK)
+		phy_writel(0xAB330031, ZQODTCTRL);
+	else if (ddr_type == RZN1_DDR3_SINGLE_BANK)
+		phy_writel(0xAB320051, ZQODTCTRL);
+	else /* DDR2 */
+		phy_writel(0xAB330071, ZQODTCTRL);
+	phy_writel(0xB545B544, RDCTRL);
+	phy_writel(0x000000B0, RDTMG);
+	phy_writel(0x020A0806, OUTCTRL);
+	if (ddr_type == RZN1_DDR3_DUAL_BANK)
+		phy_writel(0x80005556, WLCTRL1);
+	else
+		phy_writel(0x80005C5D, WLCTRL1);
+	phy_writel(0x00000101, FIFOINIT);
+	phy_writel(0x00004545, DQCALOFS1);
+
+	/* Step 9 MDLL reset release */
+	val = phy_readl(DLLCTRL);
+	val &= ~DLLCTRL_MDLLSTBY;
+	phy_writel(val, DLLCTRL);
+
+	/* Step 12 Soft reset release */
+	val = phy_readl(FUNCCTRL);
+	val |= FUNCCTRL_RESET_N;
+	phy_writel(val, FUNCCTRL);
+
+	/* Step 13 FIFO pointer initialize */
+	phy_writel(FIFOINIT_RDPTINITEXE | FIFOINIT_WRPTINITEXE, FIFOINIT);
+
+	/* Step 14 Execute ZQ Calibration */
+	val = phy_readl(ZQCALCTRL);
+	val |= ZQCALCTRL_ZQCALRSTB;
+	phy_writel(val, ZQCALCTRL);
+
+	/* Step 15 Wait for 200us or more, or wait for DFIINITCOMPLETE to be "1" */
+	while (!(phy_readl(DLLCTRL) & DLLCTRL_ASDLLOCK))
+		;
+	while (!(phy_readl(ZQCALCTRL) & ZQCALCTRL_ZQCALEND))
+		;
+
+	/* Step 16 Enable Address and Command output */
+	val = phy_readl(OUTCTRL);
+	val |= OUTCTRL_ADCMDOE;
+	phy_writel(val, OUTCTRL);
+
+	/* Step 17 Wait for 200us or more(from MRESETB=0) */
+	udelay(200);
+}
+
+static void ddr_phy_enable_wl(struct cadence_ddr_info *priv)
+{
+	u32 val;
+
+	/* Step 26 (Set Write Leveling) */
+	val = phy_readl(WLCTRL1);
+	val |= WLCTRL1_WLSTR;
+	phy_writel(val, WLCTRL1);
+}
+
+#define RZN1_V_DDR_BASE               0x80000000      /* RZ/N1D only */
+
+static void rzn1_ddr3_single_bank(void *ddr_ctrl_base)
+{
+	/* CS0 */
+	cdns_ddr_set_mr1(ddr_ctrl_base, 0,
+			 MR1_ODT_IMPEDANCE_60_OHMS,
+			 MR1_DRIVE_STRENGTH_40_OHMS);
+	cdns_ddr_set_mr2(ddr_ctrl_base, 0,
+			 MR2_DYNAMIC_ODT_OFF,
+			 MR2_SELF_REFRESH_TEMP_EXT);
+
+	/* ODT_WR_MAP_CS0 = 1, ODT_RD_MAP_CS0 = 0 */
+	cdns_ddr_set_odt_map(ddr_ctrl_base, 0, 0x0100);
+}
+
+static int rzn1_dram_init(struct cadence_ddr_info *priv)
+{
+	u32 version;
+	u32 ddr_start_addr = 0;
+
+	ddr_phy_init(priv, RZN1_DDR3_SINGLE_BANK);
+
+	/*
+	 * Override DDR PHY Interface (DFI) related settings
+	 * DFI is the internal interface between the DDR controller and the DDR PHY.
+	 * These settings are specific to the board and can't be known by the settings
+	 * provided for each DDR model within the generated include.
+	 */
+	priv->reg350[351 - 350] = 0x001e0000;
+	priv->reg350[352 - 350] = 0x1e680000;
+	priv->reg350[353 - 350] = 0x02000020;
+	priv->reg350[354 - 350] = 0x02000200;
+	priv->reg350[355 - 350] = 0x00000c30;
+	priv->reg350[356 - 350] = 0x00009808;
+	priv->reg350[357 - 350] = 0x020a0706;
+	priv->reg350[372 - 350] = 0x01000000;
+
+	/*
+	 * On ES1.0 devices, the DDR start address that the DDR Controller sees
+	 * is the physical address of the DDR. However, later devices changed it
+	 * to be 0 in order to fix an issue with DDR out-of-range detection.
+	 */
+#define RZN1_SYSCTRL_REG_VERSION 412
+	regmap_read(priv->syscon, RZN1_SYSCTRL_REG_VERSION, &version);
+	if (version == 0x10)
+		ddr_start_addr = RZN1_V_DDR_BASE;
+
+	if (priv->enable_ecc)
+		priv->ddr_size = priv->ddr_size / 2;
+
+	/* DDR Controller is always in ASYNC mode */
+	cdns_ddr_ctrl_init(priv->ddrc, 1,
+			   priv->reg0, priv->reg350,
+			   ddr_start_addr, priv->ddr_size,
+			   priv->enable_ecc, priv->enable_8bit);
+
+	rzn1_ddr3_single_bank(priv->ddrc);
+	cdns_ddr_set_diff_cs_delays(priv->ddrc, 2, 7, 2, 2);
+	cdns_ddr_set_same_cs_delays(priv->ddrc, 0, 7, 0, 0);
+	cdns_ddr_set_odt_times(priv->ddrc, 5, 6, 6, 0, 4);
+	cdns_ddr_ctrl_start(priv->ddrc);
+
+	ddr_phy_enable_wl(priv);
+
+	if (priv->enable_ecc) {
+		/*
+		 * Any read before a write will trigger an ECC un-correctable error,
+		 * causing a data abort. However, this is also true for any read with a
+		 * size less than the AXI bus width. So, the only sensible solution is
+		 * to write to all of DDR now and take the hit...
+		 */
+		memset((void *)RZN1_V_DDR_BASE, 0xff, priv->ddr_size);
+	}
+
+	return 0;
+}
+
+static int cadence_ddr_get_info(struct udevice *udev, struct ram_info *info)
+{
+	info->base = 0;
+	info->size = gd->ram_size;
+
+	return 0;
+}
+
+static struct ram_ops cadence_ddr_ops = {
+	.get_info = cadence_ddr_get_info,
+};
+
+static int cadence_ddr_test(long *base, long maxsize)
+{
+	volatile long *addr = base;
+	long           cnt;
+
+	maxsize /= sizeof(long);
+
+	for (cnt = 1; cnt <= maxsize; cnt <<= 1) {
+		addr[cnt - 1] = ~cnt;
+	}
+
+	for (cnt = 1; cnt <= maxsize; cnt <<= 1) {
+		if (addr[cnt - 1] != ~cnt) {
+			return 0;
+		}
+	}
+
+	return 1;
+}
+
+static int cadence_ddr_probe(struct udevice *dev)
+{
+	struct cadence_ddr_info *priv = dev_get_priv(dev);
+	ofnode subnode;
+	int ret;
+
+	priv->dev = dev;
+
+	priv->ddrc = dev_remap_addr_name(dev, "ddrc");
+	if (!priv->ddrc) {
+		dev_err(dev, "No reg property for Cadence DDR CTRL\n");
+		return -EINVAL;
+	}
+
+	priv->phy = dev_remap_addr_name(dev, "phy");
+	if (!priv->phy) {
+		dev_err(dev, "No reg property for Cadence DDR PHY\n");
+		return -EINVAL;
+	}
+
+	ret = clk_get_by_name(dev, "clk_ddrc", &priv->clk_ddrc);
+	if (ret) {
+		dev_err(dev, "No clock for Cadence DDR\n");
+		return ret;
+	}
+
+	ret = clk_get_by_name(dev, "hclk_ddrc", &priv->hclk_ddrc);
+	if (ret) {
+		dev_err(dev, "No HCLK for Cadence DDR\n");
+		return ret;
+	}
+
+	priv->syscon = syscon_regmap_lookup_by_phandle(dev, "syscon");
+	if (IS_ERR(priv->syscon)) {
+		dev_err(dev, "No syscon node found\n");
+		return PTR_ERR(priv->syscon);
+	}
+
+	priv->enable_ecc = dev_read_bool(dev, "enable-ecc");
+	priv->enable_8bit = dev_read_bool(dev, "enable-8bit");
+
+	priv->reg0 = malloc(88 * sizeof(u32));
+	priv->reg350 = malloc(25 * sizeof(u32));
+	if (!priv->reg0 || !priv->reg350)
+		panic("malloc failure\n");
+
+	/* There may be multiple DDR configurations to try */
+	dev_for_each_subnode(subnode, dev) {
+		ret = ofnode_read_u32(subnode, "size", &priv->ddr_size);
+		if (ret) {
+			dev_err(dev, "No size for Cadence DDR\n");
+			continue;
+		}
+
+		ret = ofnode_read_u32_array(subnode, "cadence,ctl-000", priv->reg0, 88);
+		if (ret) {
+			dev_err(dev, "No cadence,ctl-000\n");
+			continue;
+		}
+
+		ret = ofnode_read_u32_array(subnode, "cadence,ctl-350", priv->reg350, 25);
+		if (ret) {
+			dev_err(dev, "No cadence,ctl-350\n");
+			continue;
+		}
+
+		if (rzn1_dram_init(priv))
+			continue;
+
+		if (cadence_ddr_test((long *)RZN1_V_DDR_BASE, priv->ddr_size)) {
+			gd->ram_base = RZN1_V_DDR_BASE;
+			gd->ram_size = priv->ddr_size;
+			break;
+		}
+	}
+
+	if (!priv->ddr_size)
+		panic("No valid DDR to start");
+
+	free(priv->reg350);
+	free(priv->reg0);
+
+	return 0;
+}
+
+static const struct udevice_id cadence_ddr_ids[] = {
+	{ .compatible = "cadence,ddr-ctrl" },
+	{ }
+};
+
+U_BOOT_DRIVER(cadence_ddr) = {
+	.name		= "cadence_ddr",
+	.id		= UCLASS_RAM,
+	.of_match	= cadence_ddr_ids,
+	.ops		= &cadence_ddr_ops,
+	.probe		= cadence_ddr_probe,
+	.priv_auto	= sizeof(struct cadence_ddr_info),
+	.flags		= DM_FLAG_PRE_RELOC,
+};
diff --git a/board/schneider/rzn1-snarc/rzn1.c b/board/schneider/rzn1-snarc/rzn1.c
new file mode 100644
index 0000000000..6eb86c2592
--- /dev/null
+++ b/board/schneider/rzn1-snarc/rzn1.c
@@ -0,0 +1,40 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <dm.h>
+#include <ram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/*
+	 * Initial values for gd->ram_base and gd->ram_size
+	 * are obtained from the "/memory" node in devicetree.
+	 * The size will be updated in later when probing DDR.
+	 */
+	fdtdec_setup_mem_size_base();
+
+	gd->bd->bi_boot_params = gd->ram_base + 0x100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	struct udevice *dev;
+	int err;
+
+	/*
+	 * This will end up calling cadence_ddr_probe(),
+	 * and will also update gd->ram_size.
+	 */
+	err = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (err) {
+		debug("DRAM init failed: %d\n", err);
+		return err;
+	}
+
+	return 0;
+}
diff --git a/configs/rzn1_snarc_defconfig b/configs/rzn1_snarc_defconfig
new file mode 100644
index 0000000000..eb52aa3c8a
--- /dev/null
+++ b/configs/rzn1_snarc_defconfig
@@ -0,0 +1,24 @@ 
+CONFIG_ARM=y
+CONFIG_SYS_ARCH_TIMER=y
+CONFIG_SYS_THUMB_BUILD=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_MALLOC_LEN=0xb0000
+CONFIG_SYS_MALLOC_F_LEN=0x800
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="r9a06g032-rzn1-snarc"
+CONFIG_RZN1=y
+CONFIG_SYS_LOAD_ADDR=0x80008000
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x8fffffff
+# CONFIG_ARCH_MISC_INIT is not set
+# CONFIG_BOARD_EARLY_INIT_F is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+# CONFIG_SYS_ALT_MEMTEST_BITFLIP is not set
+CONFIG_CMD_CLK=y
+CONFIG_OF_CONTROL=y
+CONFIG_RAM=y
+CONFIG_CADENCE_DDR_CTRL=y
+CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_MEM32=y
+# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/rzn1-snarc.h b/include/configs/rzn1-snarc.h
new file mode 100644
index 0000000000..dce0de0d4c
--- /dev/null
+++ b/include/configs/rzn1-snarc.h
@@ -0,0 +1,13 @@ 
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration settings for the Schneider RZ/N1 board
+ */
+
+#ifndef __RZN1_H
+#define __RZN1_H
+
+/* Internal RAM */
+#define CFG_SYS_INIT_RAM_ADDR	0x20000000
+#define CFG_SYS_INIT_RAM_SIZE	(1 * 1024 * 1024)
+
+#endif	/* __RZN1_H */
diff --git a/include/renesas/is43tr16256a_125k_CTL.h b/include/renesas/is43tr16256a_125k_CTL.h
new file mode 100644
index 0000000000..fabc2c7b79
--- /dev/null
+++ b/include/renesas/is43tr16256a_125k_CTL.h
@@ -0,0 +1,419 @@ 
+
+/* ****************************************************************
+ *        CADENCE                    Copyright (c) 2001-2011      *
+ *                                   Cadence Design Systems, Inc. *
+ *                                   All rights reserved.         *
+ *                                                                *
+ ******************************************************************
+ *  The values calculated from this script are meant to be        *
+ *  representative programmings.   The values may not reflect the *
+ *  actual required programming for production use.   Please      *
+ *  closely review all programmed values for technical accuracy   *
+ *  before use in production parts.                               *
+ ******************************************************************
+ *
+ *   Module:         regconfig.h
+ *   Documentation:  Register programming header file
+ *
+ ******************************************************************
+ ******************************************************************
+ * WARNING:  This file was automatically generated.  Manual
+ * editing may result in undetermined behavior.
+ ******************************************************************
+ ******************************************************************/
+// REL: renesas.germany-LCES_DDR__2014-05-21
+
+// ********************************************************************
+// Option: IP    : IP Mode                       = CTL
+// Option: BL    : Burst Length                  = 8
+// Option: CL    : CAS Latency                   = 8
+// Option: MHZ   : Simulation MHz                = 500
+// Option: AP    : Auto Precharge Mode     (0/1) = 0
+// Option: DLLBP : DLL Bypass Mode         (0/1) = 1
+// Option: HALF  : Half-Memory Support     (0/1) = 0
+// Option: RDIMM : Registered Dimm Support (0/1) = 0
+// Option: AL    : Additive Latency              = 0
+// Option: RSV3  : Reserved                  (0) = 0
+// Option: TCK   : Simulation period in ns       =
+// Option: RDDBIEN : Read DBI Enable       (0/1) = 0
+// Option: SOMA  : Memory-SOMA file(s)           = is43tr16256a_125k_xml.soma
+// ********************************************************************
+// Memory: is43tr16256a_125k_xml.soma
+// ********************************************************************
+
+#define DENALI_CTL_00_DATA	0x00000600 // VERSION:RD:16:16:=0x0000 DRAM_CLASS:RW:8:4:=0x06 START:RW:0:1:=0x00
+#define DENALI_CTL_01_DATA	0x00000000 // READ_DATA_FIFO_DEPTH:RD:24:8:=0x00 MAX_CS_REG:RD:16:2:=0x00 MAX_COL_REG:RD:8:4:=0x00 MAX_ROW_REG:RD:0:5:=0x00
+#define DENALI_CTL_02_DATA	0x00000000 // ASYNC_CDC_STAGES:RD:24:8:=0x00 WRITE_DATA_FIFO_PTR_WIDTH:RD:16:8:=0x00 WRITE_DATA_FIFO_DEPTH:RD:8:8:=0x00 READ_DATA_FIFO_PTR_WIDTH:RD:0:8:=0x00
+#define DENALI_CTL_03_DATA	0x00000000 // AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI0_WRFIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI0_RDFIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI0_CMDFIFO_LOG2_DEPTH:RD:0:8:=0x00
+#define DENALI_CTL_04_DATA	0x00000000 // AXI1_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI1_WRFIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI1_RDFIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI1_CMDFIFO_LOG2_DEPTH:RD:0:8:=0x00
+#define DENALI_CTL_05_DATA	0x00000000 // AXI2_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI2_WRFIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI2_RDFIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI2_CMDFIFO_LOG2_DEPTH:RD:0:8:=0x00
+#define DENALI_CTL_06_DATA	0x00000000 // AXI3_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI3_WRFIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI3_RDFIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI3_CMDFIFO_LOG2_DEPTH:RD:0:8:=0x00
+#define DENALI_CTL_07_DATA	0x00000005 // TINIT:RW:0:24:=0x000005
+#define DENALI_CTL_08_DATA	0x000186a0 // TRST_PWRON:RW:0:32:=0x000186a0
+#define DENALI_CTL_09_DATA	0x0003d090 // CKE_INACTIVE:RW:0:32:=0x0003d090
+#define DENALI_CTL_10_DATA	0x00000000 // TCPD:RW:8:16:=0x0000 INITAREF:RW:0:4:=0x00
+#define DENALI_CTL_11_DATA	0x10000200 // CASLAT_LIN:RW:24:6:=0x10 NO_CMD_INIT:RW:16:1:=0x00 TDLL:RW:0:16:=0x0200
+#define DENALI_CTL_12_DATA	0x04040006 // TCCD:RW:24:5:=0x04 TBST_INT_INTERVAL:RW:16:3:=0x04 ADDITIVE_LAT:RW:8:5:=0x00 WRLAT:RW:0:5:=0x06
+#define DENALI_CTL_13_DATA	0x04121904 // TWTR:RW:24:6:=0x04 TRAS_MIN:RW:16:8:=0x12 TRC:RW:8:8:=0x19 TRRD:RW:0:8:=0x04
+#define DENALI_CTL_14_DATA	0x04041407 // TMRD:RW:24:5:=0x04 TRTP:RW:16:4:=0x04 TFAW:RW:8:6:=0x14 TRP:RW:0:5:=0x07
+#define DENALI_CTL_15_DATA	0x00891c0c // TRAS_MAX:RW:8:17:=0x00891c TMOD:RW:0:8:=0x0c
+#define DENALI_CTL_16_DATA	0x07000503 // TRCD:RW:24:8:=0x07 WRITEINTERP:RW:16:1:=0x00 TCKESR:RW:8:8:=0x05 TCKE:RW:0:3:=0x03
+#define DENALI_CTL_17_DATA	0x01010008 // TRAS_LOCKOUT:RW:24:1:=0x01 CONCURRENTAP:RW:16:1:=0x01 AP:RW:8:1:=0x00 TWR:RW:0:6:=0x08
+#define DENALI_CTL_18_DATA	0x0007030f // REG_DIMM_ENABLE:RW:24:1:=0x00 TRP_AB:RW:16:5:=0x07 BSTLEN:RW_D:8:3:=0x03 TDAL:RW:0:6:=0x0f
+#define DENALI_CTL_19_DATA	0x01000000 // TREF_ENABLE:RW:24:1:=0x01 RESERVED:RW:16:1:=0x00 AREFRESH:WR:8:1:=0x00 ADDRESS_MIRRORING:RW:0:2:=0x00
+#define DENALI_CTL_20_DATA	0x0f340082 // TREF:RW:16:14:=0x0f34 TRFC:RW:0:10:=0x0082
+#define DENALI_CTL_21_DATA	0x00000005 // TREF_INTERVAL:RW:0:14:=0x0005
+#define DENALI_CTL_22_DATA	0x000c0003 // TXPDLL:RW:16:16:=0x000c TPDEX:RW:0:16:=0x0003
+#define DENALI_CTL_23_DATA	0x00000000 // TXARDS:RW:16:16:=0x0000 TXARD:RW:0:16:=0x0000
+#define DENALI_CTL_24_DATA	0x00870200 // TXSNR:RW:16:16:=0x0087 TXSR:RW:0:16:=0x0200
+#define DENALI_CTL_25_DATA	0x00010000 // CKE_DELAY:RW:24:3:=0x00 ENABLE_QUICK_SREFRESH:RW:16:1:=0x01 SREFRESH_EXIT_NO_REFRESH:RW:8:1:=0x00 PWRUP_SREFRESH_EXIT:RW:0:1:=0x00
+#define DENALI_CTL_26_DATA	0x00050500 // LP_CMD:WR:24:8:=0x00 CKSRX:RW:16:8:=0x05 CKSRE:RW:8:8:=0x05 LOWPOWER_REFRESH_ENABLE:RW:0:2:=0x00
+#define DENALI_CTL_27_DATA	0x00000000 // LP_AUTO_EXIT_EN:RW:24:3:=0x00 LP_AUTO_ENTRY_EN:RW:16:3:=0x00 LP_ARB_STATE:RD:8:4:=0x00 LP_STATE:RD:0:6:=0x00
+#define DENALI_CTL_28_DATA	0x00000000 // LP_AUTO_SR_IDLE:RW:24:8:=0x00 LP_AUTO_PD_IDLE:RW:8:12:=0x0000 LP_AUTO_MEM_GATE_EN:RW:0:2:=0x00
+#define DENALI_CTL_29_DATA	0x00000000 // RESERVED:RW:8:7:=0x00 LP_AUTO_SR_MC_GATE_IDLE:RW:0:8:=0x00
+#define DENALI_CTL_30_DATA	0x00000000 // WRITE_MODEREG:RW+:0:26:=0x00000000
+#define DENALI_CTL_31_DATA	0x00084000 // MR0_DATA_0:RW:8:16:=0x0840 MRW_STATUS:RD:0:8:=0x00
+#define DENALI_CTL_32_DATA	0x00080046 // MR2_DATA_0:RW:16:16:=0x0008 MR1_DATA_0:RW:0:16:=0x0046
+#define DENALI_CTL_33_DATA	0x00000000 // MR3_DATA_0:RW:16:16:=0x0000 MRSINGLE_DATA_0:RW:0:16:=0x0000
+#define DENALI_CTL_34_DATA	0x00460840 // MR1_DATA_1:RW:16:16:=0x0046 MR0_DATA_1:RW:0:16:=0x0840
+#define DENALI_CTL_35_DATA	0x00000008 // MRSINGLE_DATA_1:RW:16:16:=0x0000 MR2_DATA_1:RW:0:16:=0x0008
+#define DENALI_CTL_36_DATA	0x00010000 // FWC:WR:24:1:=0x00 ECC_EN:RW:16:1:=0x01 MR3_DATA_1:RW:0:16:=0x0000
+#define DENALI_CTL_37_DATA	0x00000000 // ECC_DISABLE_W_UC_ERR:RW:16:1:=0x00 XOR_CHECK_BITS:RW:0:14:=0x0000
+#define DENALI_CTL_38_DATA	0x00000000 // ECC_U_ADDR:RD:0:32:=0x00000000
+#define DENALI_CTL_39_DATA	0x00000000 // ECC_U_SYND:RD:0:7:=0x00
+#define DENALI_CTL_40_DATA	0x00000000 // ECC_U_DATA:RD:0:32:=0x00000000
+#define DENALI_CTL_41_DATA	0x00000000 // ECC_C_ADDR:RD:0:32:=0x00000000
+#define DENALI_CTL_42_DATA	0x00000000 // ECC_C_SYND:RD:0:7:=0x00
+#define DENALI_CTL_43_DATA	0x00000000 // ECC_C_DATA:RD:0:32:=0x00000000
+#define DENALI_CTL_44_DATA	0x00000000 // LONG_COUNT_MASK:RW:16:5:=0x00 ECC_C_ID:RD:8:6:=0x00 ECC_U_ID:RD:0:6:=0x00
+#define DENALI_CTL_45_DATA	0x01000200 // ZQCL:RW:16:12:=0x0100 ZQINIT:RW_D:0:12:=0x0200
+#define DENALI_CTL_46_DATA	0x02000040 // ZQ_ON_SREF_EXIT:RW:24:2:=0x02 ZQ_REQ:WR:16:2:=0x00 ZQCS:RW:0:12:=0x0040
+#define DENALI_CTL_47_DATA	0x00000040 // ZQ_INTERVAL:RW:0:32:=0x00000040
+#define DENALI_CTL_48_DATA	0x01000100 // ROW_DIFF:RW:24:3:=0x01 BANK_DIFF:RW:16:2:=0x00 ZQCS_ROTATE:RW:8:1:=0x01 ZQ_IN_PROGRESS:RD:0:1:=0x00
+#define DENALI_CTL_49_DATA	0xffff0a01 // COMMAND_AGE_COUNT:RW:24:8:=0xff AGE_COUNT:RW:16:8:=0xff APREBIT:RW_D:8:4:=0x0a COL_DIFF:RW:0:4:=0x01
+#define DENALI_CTL_50_DATA	0x01010101 // PLACEMENT_EN:RW:24:1:=0x01 BANK_SPLIT_EN:RW:16:1:=0x01 RESERVED:RW:8:1:=0x01 ADDR_CMP_EN:RW:0:1:=0x01
+#define DENALI_CTL_51_DATA	0x01010101 // CS_SAME_EN:RW:24:1:=0x01 RW_SAME_PAGE_EN:RW:16:1:=0x01 RW_SAME_EN:RW:8:1:=0x01 PRIORITY_EN:RW:0:1:=0x01
+#define DENALI_CTL_52_DATA	0x01030101 // SWAP_EN:RW:24:1:=0x01 NUM_Q_ENTRIES_ACT_DISABLE:RW:16:3:=0x03 DISABLE_RW_GROUP_W_BNK_CONFLICT:RW:8:2:=0x01 W2R_SPLIT_EN:RW:0:1:=0x01
+#define DENALI_CTL_53_DATA	0x0c030000 // BURST_ON_FLY_BIT:RW:24:4:=0x0c CS_MAP:RW:16:2:=0x03 INHIBIT_DRAM_CMD:RW:8:1:=0x00 DISABLE_RD_INTERLEAVE:RW:0:1:=0x00
+#define DENALI_CTL_54_DATA	0x00000000 // CONTROLLER_BUSY:RD:24:1:=0x00 IN_ORDER_ACCEPT:RW:16:1:=0x00 Q_FULLNESS:RW:8:3:=0x00 REDUC:RW:0:1:=0x00
+#define DENALI_CTL_55_DATA	0x00000100 // CTRLUPD_REQ_PER_AREF_EN:RW:8:1:=0x01 CTRLUPD_REQ:WR:0:1:=0x00
+#define DENALI_CTL_56_DATA	0x00000000 // INT_STATUS:RD:0:23:=0x000000
+#define DENALI_CTL_57_DATA	0x00000000 // INT_ACK:WR:0:22:=0x000000
+#define DENALI_CTL_58_DATA	0x00000000 // INT_MASK:RW:0:23:=0x000000
+#define DENALI_CTL_59_DATA	0x00000000 // OUT_OF_RANGE_ADDR:RD:0:32:=0x00000000
+#define DENALI_CTL_60_DATA	0x00000000 // OUT_OF_RANGE_SOURCE_ID:RD:16:6:=0x00 OUT_OF_RANGE_TYPE:RD:8:6:=0x00 OUT_OF_RANGE_LENGTH:RD:0:7:=0x00
+#define DENALI_CTL_61_DATA	0x00000000 // PORT_CMD_ERROR_ADDR:RD:0:32:=0x00000000
+#define DENALI_CTL_62_DATA	0x01020000 // ODT_WR_MAP_CS0:RW:24:2:=0x01 ODT_RD_MAP_CS0:RW:16:2:=0x02 PORT_CMD_ERROR_TYPE:RD:8:3:=0x00 PORT_CMD_ERROR_ID:RD:0:6:=0x00
+#define DENALI_CTL_63_DATA	0x06050201 // TODTH_WR:RW:24:4:=0x06 TODTL_2CMD:RW:16:8:=0x05 ODT_WR_MAP_CS1:RW:8:2:=0x02 ODT_RD_MAP_CS1:RW:0:2:=0x01
+#define DENALI_CTL_64_DATA	0x02000106 // RD_TO_ODTH:RW:24:7:=0x02 WR_TO_ODTH:RW:16:7:=0x00 ODT_EN:RW:8:1:=0x01 TODTH_RD:RW:0:4:=0x06
+#define DENALI_CTL_65_DATA	0x00000000 //
+#define DENALI_CTL_66_DATA	0x02020202 // W2W_DIFFCS_DLY:RW_D:24:4:=0x02 W2R_DIFFCS_DLY:RW_D:16:3:=0x02 R2W_DIFFCS_DLY:RW_D:8:3:=0x02 R2R_DIFFCS_DLY:RW_D:0:3:=0x02
+#define DENALI_CTL_67_DATA	0x00000200 // W2W_SAMECS_DLY:RW:24:3:=0x00 W2R_SAMECS_DLY:RW:16:3:=0x00 R2W_SAMECS_DLY:RW_D:8:3:=0x02 R2R_SAMECS_DLY:RW:0:3:=0x00
+#define DENALI_CTL_68_DATA	0x00000000 // SWLVL_LOAD:WR:24:1:=0x00 SW_LEVELING_MODE:RW:16:2:=0x00 OCD_ADJUST_PUP_CS_0:RW:8:5:=0x00 OCD_ADJUST_PDN_CS_0:RW:0:5:=0x00
+#define DENALI_CTL_69_DATA	0x00000000 // LVL_STATUS:RD:24:4:=0x00 SWLVL_OP_DONE:RD:16:1:=0x00 SWLVL_EXIT:WR:8:1:=0x00 SWLVL_START:WR:0:1:=0x00
+#define DENALI_CTL_70_DATA	0x00000000 // WRLVL_REQ:WR:24:1:=0x00 SWLVL_RESP_2:RD:16:8:=0x00 SWLVL_RESP_1:RD:8:8:=0x00 SWLVL_RESP_0:RD:0:8:=0x00
+#define DENALI_CTL_71_DATA	0x00280d00 // WRLVL_EN:RW:24:1:=0x00 WLMRD:RW:16:6:=0x28 WLDQSEN:RW:8:6:=0x0d WRLVL_CS:RW:0:1:=0x00
+#define DENALI_CTL_72_DATA	0x00000000 // WRLVL_ERROR_STATUS:RD:24:8:=0x00 RESERVED:RW:16:3:=0x00 WRLVL_INTERVAL:RW:0:16:=0x0000
+#define DENALI_CTL_73_DATA	0x00000100 // WRLVL_DELAY_0:RW+:8:16:=0x0001 WRLVL_REG_EN:RW:0:1:=0x00
+#define DENALI_CTL_74_DATA	0x00010001 // WRLVL_DELAY_2:RW+:16:16:=0x0001 WRLVL_DELAY_1:RW+:0:16:=0x0001
+#define DENALI_CTL_75_DATA	0x00000000 // RDLVL_EDGE:RW:24:1:=0x00 RDLVL_CS:RW:16:1:=0x00 RDLVL_GATE_REQ:WR:8:1:=0x00 RDLVL_REQ:WR:0:1:=0x00
+#define DENALI_CTL_76_DATA	0x00000000 // RDLVL_GATE_REG_EN:RW:16:1:=0x00 RDLVL_REG_EN:RW:8:1:=0x00 RDLVL_BEGIN_DELAY_EN:RW:0:1:=0x00
+#define DENALI_CTL_77_DATA	0x00000000 // RDLVL_END_DELAY_0:RD:16:16:=0x0000 RDLVL_BEGIN_DELAY_0:RD:0:16:=0x0000
+#define DENALI_CTL_78_DATA	0x00000000 // RDLVL_OFFSET_DELAY_0:RW:16:16:=0x0000 RDLVL_MIDPOINT_DELAY_0:RD:0:16:=0x0000
+#define DENALI_CTL_79_DATA	0x00212100 // RDLVL_DELAY_0:RW:8:16:=0x2121 RDLVL_OFFSET_DIR_0:RW:0:1:=0x00
+#define DENALI_CTL_80_DATA	0x00000001 // RDLVL_BEGIN_DELAY_1:RD:16:16:=0x0000 RDLVL_GATE_DELAY_0:RW+:0:16:=0x0001
+#define DENALI_CTL_81_DATA	0x00000000 // RDLVL_MIDPOINT_DELAY_1:RD:16:16:=0x0000 RDLVL_END_DELAY_1:RD:0:16:=0x0000
+#define DENALI_CTL_82_DATA	0x00000000 // RDLVL_OFFSET_DIR_1:RW:16:1:=0x00 RDLVL_OFFSET_DELAY_1:RW:0:16:=0x0000
+#define DENALI_CTL_83_DATA	0x00012121 // RDLVL_GATE_DELAY_1:RW+:16:16:=0x0001 RDLVL_DELAY_1:RW:0:16:=0x2121
+#define DENALI_CTL_84_DATA	0x00000000 // RDLVL_END_DELAY_2:RD:16:16:=0x0000 RDLVL_BEGIN_DELAY_2:RD:0:16:=0x0000
+#define DENALI_CTL_85_DATA	0x00000000 // RDLVL_OFFSET_DELAY_2:RW:16:16:=0x0000 RDLVL_MIDPOINT_DELAY_2:RD:0:16:=0x0000
+#define DENALI_CTL_86_DATA	0x00212100 // RDLVL_DELAY_2:RW:8:16:=0x2121 RDLVL_OFFSET_DIR_2:RW:0:1:=0x00
+#define DENALI_CTL_87_DATA	0x02020001 // AXI0_W_PRIORITY:RW:24:2:=0x02 AXI0_R_PRIORITY:RW:16:2:=0x02 RDLVL_GATE_DELAY_2:RW+:0:16:=0x0001
+#define DENALI_CTL_88_DATA	0x00020200 // AXI1_FIFO_TYPE_REG:RW:24:2:=0x00 AXI1_W_PRIORITY:RW:16:2:=0x02 AXI1_R_PRIORITY:RW:8:2:=0x02 AXI0_FIFO_TYPE_REG:RW:0:2:=0x00
+#define DENALI_CTL_89_DATA	0x02000202 // AXI3_R_PRIORITY:RW:24:2:=0x02 AXI2_FIFO_TYPE_REG:RW:16:2:=0x00 AXI2_W_PRIORITY:RW:8:2:=0x02 AXI2_R_PRIORITY:RW:0:2:=0x02
+#define DENALI_CTL_90_DATA	0x01000002 // PORT_ADDR_PROTECTION_EN:RW:24:1:=0x01 AXI3_FIFO_TYPE_REG:RW:8:2:=0x00 AXI3_W_PRIORITY:RW:0:2:=0x02
+#define DENALI_CTL_91_DATA	0x00000000 // AXI0_START_ADDR_0:RW:0:18:=0x000000
+#define DENALI_CTL_92_DATA	0x0003ffff // AXI0_END_ADDR_0:RW:0:18:=0x03ffff
+#define DENALI_CTL_93_DATA	0x00000000 // AXI0_START_ADDR_1:RW:0:18:=0x000000
+#define DENALI_CTL_94_DATA	0x0003ffff // AXI0_END_ADDR_1:RW:0:18:=0x03ffff
+#define DENALI_CTL_95_DATA	0x00000000 // AXI0_START_ADDR_2:RW:0:18:=0x000000
+#define DENALI_CTL_96_DATA	0x0003ffff // AXI0_END_ADDR_2:RW:0:18:=0x03ffff
+#define DENALI_CTL_97_DATA	0x00000000 // AXI0_START_ADDR_3:RW:0:18:=0x000000
+#define DENALI_CTL_98_DATA	0x0003ffff // AXI0_END_ADDR_3:RW:0:18:=0x03ffff
+#define DENALI_CTL_99_DATA	0x00000000 // AXI0_START_ADDR_4:RW:0:18:=0x000000
+#define DENALI_CTL_100_DATA	0x0003ffff // AXI0_END_ADDR_4:RW:0:18:=0x03ffff
+#define DENALI_CTL_101_DATA	0x00000000 // AXI0_START_ADDR_5:RW:0:18:=0x000000
+#define DENALI_CTL_102_DATA	0x0003ffff // AXI0_END_ADDR_5:RW:0:18:=0x03ffff
+#define DENALI_CTL_103_DATA	0x00000000 // AXI0_START_ADDR_6:RW:0:18:=0x000000
+#define DENALI_CTL_104_DATA	0x0003ffff // AXI0_END_ADDR_6:RW:0:18:=0x03ffff
+#define DENALI_CTL_105_DATA	0x00000000 // AXI0_START_ADDR_7:RW:0:18:=0x000000
+#define DENALI_CTL_106_DATA	0x0003ffff // AXI0_END_ADDR_7:RW:0:18:=0x03ffff
+#define DENALI_CTL_107_DATA	0x00000000 // AXI0_START_ADDR_8:RW:0:18:=0x000000
+#define DENALI_CTL_108_DATA	0x0003ffff // AXI0_END_ADDR_8:RW:0:18:=0x03ffff
+#define DENALI_CTL_109_DATA	0x00000000 // AXI0_START_ADDR_9:RW:0:18:=0x000000
+#define DENALI_CTL_110_DATA	0x0003ffff // AXI0_END_ADDR_9:RW:0:18:=0x03ffff
+#define DENALI_CTL_111_DATA	0x00000000 // AXI0_START_ADDR_10:RW:0:18:=0x000000
+#define DENALI_CTL_112_DATA	0x0003ffff // AXI0_END_ADDR_10:RW:0:18:=0x03ffff
+#define DENALI_CTL_113_DATA	0x00000000 // AXI0_START_ADDR_11:RW:0:18:=0x000000
+#define DENALI_CTL_114_DATA	0x0003ffff // AXI0_END_ADDR_11:RW:0:18:=0x03ffff
+#define DENALI_CTL_115_DATA	0x00000000 // AXI0_START_ADDR_12:RW:0:18:=0x000000
+#define DENALI_CTL_116_DATA	0x0003ffff // AXI0_END_ADDR_12:RW:0:18:=0x03ffff
+#define DENALI_CTL_117_DATA	0x00000000 // AXI0_START_ADDR_13:RW:0:18:=0x000000
+#define DENALI_CTL_118_DATA	0x0003ffff // AXI0_END_ADDR_13:RW:0:18:=0x03ffff
+#define DENALI_CTL_119_DATA	0x00000000 // AXI0_START_ADDR_14:RW:0:18:=0x000000
+#define DENALI_CTL_120_DATA	0x0003ffff // AXI0_END_ADDR_14:RW:0:18:=0x03ffff
+#define DENALI_CTL_121_DATA	0x00000000 // AXI0_START_ADDR_15:RW:0:18:=0x000000
+#define DENALI_CTL_122_DATA	0x0003ffff // AXI0_END_ADDR_15:RW:0:18:=0x03ffff
+#define DENALI_CTL_123_DATA	0x00000000 // AXI1_START_ADDR_0:RW:0:18:=0x000000
+#define DENALI_CTL_124_DATA	0x0003ffff // AXI1_END_ADDR_0:RW:0:18:=0x03ffff
+#define DENALI_CTL_125_DATA	0x00000000 // AXI1_START_ADDR_1:RW:0:18:=0x000000
+#define DENALI_CTL_126_DATA	0x0003ffff // AXI1_END_ADDR_1:RW:0:18:=0x03ffff
+#define DENALI_CTL_127_DATA	0x00000000 // AXI1_START_ADDR_2:RW:0:18:=0x000000
+#define DENALI_CTL_128_DATA	0x0003ffff // AXI1_END_ADDR_2:RW:0:18:=0x03ffff
+#define DENALI_CTL_129_DATA	0x00000000 // AXI1_START_ADDR_3:RW:0:18:=0x000000
+#define DENALI_CTL_130_DATA	0x0003ffff // AXI1_END_ADDR_3:RW:0:18:=0x03ffff
+#define DENALI_CTL_131_DATA	0x00000000 // AXI1_START_ADDR_4:RW:0:18:=0x000000
+#define DENALI_CTL_132_DATA	0x0003ffff // AXI1_END_ADDR_4:RW:0:18:=0x03ffff
+#define DENALI_CTL_133_DATA	0x00000000 // AXI1_START_ADDR_5:RW:0:18:=0x000000
+#define DENALI_CTL_134_DATA	0x0003ffff // AXI1_END_ADDR_5:RW:0:18:=0x03ffff
+#define DENALI_CTL_135_DATA	0x00000000 // AXI1_START_ADDR_6:RW:0:18:=0x000000
+#define DENALI_CTL_136_DATA	0x0003ffff // AXI1_END_ADDR_6:RW:0:18:=0x03ffff
+#define DENALI_CTL_137_DATA	0x00000000 // AXI1_START_ADDR_7:RW:0:18:=0x000000
+#define DENALI_CTL_138_DATA	0x0003ffff // AXI1_END_ADDR_7:RW:0:18:=0x03ffff
+#define DENALI_CTL_139_DATA	0x00000000 // AXI1_START_ADDR_8:RW:0:18:=0x000000
+#define DENALI_CTL_140_DATA	0x0003ffff // AXI1_END_ADDR_8:RW:0:18:=0x03ffff
+#define DENALI_CTL_141_DATA	0x00000000 // AXI1_START_ADDR_9:RW:0:18:=0x000000
+#define DENALI_CTL_142_DATA	0x0003ffff // AXI1_END_ADDR_9:RW:0:18:=0x03ffff
+#define DENALI_CTL_143_DATA	0x00000000 // AXI1_START_ADDR_10:RW:0:18:=0x000000
+#define DENALI_CTL_144_DATA	0x0003ffff // AXI1_END_ADDR_10:RW:0:18:=0x03ffff
+#define DENALI_CTL_145_DATA	0x00000000 // AXI1_START_ADDR_11:RW:0:18:=0x000000
+#define DENALI_CTL_146_DATA	0x0003ffff // AXI1_END_ADDR_11:RW:0:18:=0x03ffff
+#define DENALI_CTL_147_DATA	0x00000000 // AXI1_START_ADDR_12:RW:0:18:=0x000000
+#define DENALI_CTL_148_DATA	0x0003ffff // AXI1_END_ADDR_12:RW:0:18:=0x03ffff
+#define DENALI_CTL_149_DATA	0x00000000 // AXI1_START_ADDR_13:RW:0:18:=0x000000
+#define DENALI_CTL_150_DATA	0x0003ffff // AXI1_END_ADDR_13:RW:0:18:=0x03ffff
+#define DENALI_CTL_151_DATA	0x00000000 // AXI1_START_ADDR_14:RW:0:18:=0x000000
+#define DENALI_CTL_152_DATA	0x0003ffff // AXI1_END_ADDR_14:RW:0:18:=0x03ffff
+#define DENALI_CTL_153_DATA	0x00000000 // AXI1_START_ADDR_15:RW:0:18:=0x000000
+#define DENALI_CTL_154_DATA	0x0003ffff // AXI1_END_ADDR_15:RW:0:18:=0x03ffff
+#define DENALI_CTL_155_DATA	0x00000000 // AXI2_START_ADDR_0:RW:0:18:=0x000000
+#define DENALI_CTL_156_DATA	0x0003ffff // AXI2_END_ADDR_0:RW:0:18:=0x03ffff
+#define DENALI_CTL_157_DATA	0x00000000 // AXI2_START_ADDR_1:RW:0:18:=0x000000
+#define DENALI_CTL_158_DATA	0x0003ffff // AXI2_END_ADDR_1:RW:0:18:=0x03ffff
+#define DENALI_CTL_159_DATA	0x00000000 // AXI2_START_ADDR_2:RW:0:18:=0x000000
+#define DENALI_CTL_160_DATA	0x0003ffff // AXI2_END_ADDR_2:RW:0:18:=0x03ffff
+#define DENALI_CTL_161_DATA	0x00000000 // AXI2_START_ADDR_3:RW:0:18:=0x000000
+#define DENALI_CTL_162_DATA	0x0003ffff // AXI2_END_ADDR_3:RW:0:18:=0x03ffff
+#define DENALI_CTL_163_DATA	0x00000000 // AXI2_START_ADDR_4:RW:0:18:=0x000000
+#define DENALI_CTL_164_DATA	0x0003ffff // AXI2_END_ADDR_4:RW:0:18:=0x03ffff
+#define DENALI_CTL_165_DATA	0x00000000 // AXI2_START_ADDR_5:RW:0:18:=0x000000
+#define DENALI_CTL_166_DATA	0x0003ffff // AXI2_END_ADDR_5:RW:0:18:=0x03ffff
+#define DENALI_CTL_167_DATA	0x00000000 // AXI2_START_ADDR_6:RW:0:18:=0x000000
+#define DENALI_CTL_168_DATA	0x0003ffff // AXI2_END_ADDR_6:RW:0:18:=0x03ffff
+#define DENALI_CTL_169_DATA	0x00000000 // AXI2_START_ADDR_7:RW:0:18:=0x000000
+#define DENALI_CTL_170_DATA	0x0003ffff // AXI2_END_ADDR_7:RW:0:18:=0x03ffff
+#define DENALI_CTL_171_DATA	0x00000000 // AXI2_START_ADDR_8:RW:0:18:=0x000000
+#define DENALI_CTL_172_DATA	0x0003ffff // AXI2_END_ADDR_8:RW:0:18:=0x03ffff
+#define DENALI_CTL_173_DATA	0x00000000 // AXI2_START_ADDR_9:RW:0:18:=0x000000
+#define DENALI_CTL_174_DATA	0x0003ffff // AXI2_END_ADDR_9:RW:0:18:=0x03ffff
+#define DENALI_CTL_175_DATA	0x00000000 // AXI2_START_ADDR_10:RW:0:18:=0x000000
+#define DENALI_CTL_176_DATA	0x0003ffff // AXI2_END_ADDR_10:RW:0:18:=0x03ffff
+#define DENALI_CTL_177_DATA	0x00000000 // AXI2_START_ADDR_11:RW:0:18:=0x000000
+#define DENALI_CTL_178_DATA	0x0003ffff // AXI2_END_ADDR_11:RW:0:18:=0x03ffff
+#define DENALI_CTL_179_DATA	0x00000000 // AXI2_START_ADDR_12:RW:0:18:=0x000000
+#define DENALI_CTL_180_DATA	0x0003ffff // AXI2_END_ADDR_12:RW:0:18:=0x03ffff
+#define DENALI_CTL_181_DATA	0x00000000 // AXI2_START_ADDR_13:RW:0:18:=0x000000
+#define DENALI_CTL_182_DATA	0x0003ffff // AXI2_END_ADDR_13:RW:0:18:=0x03ffff
+#define DENALI_CTL_183_DATA	0x00000000 // AXI2_START_ADDR_14:RW:0:18:=0x000000
+#define DENALI_CTL_184_DATA	0x0003ffff // AXI2_END_ADDR_14:RW:0:18:=0x03ffff
+#define DENALI_CTL_185_DATA	0x00000000 // AXI2_START_ADDR_15:RW:0:18:=0x000000
+#define DENALI_CTL_186_DATA	0x0003ffff // AXI2_END_ADDR_15:RW:0:18:=0x03ffff
+#define DENALI_CTL_187_DATA	0x00000000 // AXI3_START_ADDR_0:RW:0:18:=0x000000
+#define DENALI_CTL_188_DATA	0x0003ffff // AXI3_END_ADDR_0:RW:0:18:=0x03ffff
+#define DENALI_CTL_189_DATA	0x00000000 // AXI3_START_ADDR_1:RW:0:18:=0x000000
+#define DENALI_CTL_190_DATA	0x0003ffff // AXI3_END_ADDR_1:RW:0:18:=0x03ffff
+#define DENALI_CTL_191_DATA	0x00000000 // AXI3_START_ADDR_2:RW:0:18:=0x000000
+#define DENALI_CTL_192_DATA	0x0003ffff // AXI3_END_ADDR_2:RW:0:18:=0x03ffff
+#define DENALI_CTL_193_DATA	0x00000000 // AXI3_START_ADDR_3:RW:0:18:=0x000000
+#define DENALI_CTL_194_DATA	0x0003ffff // AXI3_END_ADDR_3:RW:0:18:=0x03ffff
+#define DENALI_CTL_195_DATA	0x00000000 // AXI3_START_ADDR_4:RW:0:18:=0x000000
+#define DENALI_CTL_196_DATA	0x0003ffff // AXI3_END_ADDR_4:RW:0:18:=0x03ffff
+#define DENALI_CTL_197_DATA	0x00000000 // AXI3_START_ADDR_5:RW:0:18:=0x000000
+#define DENALI_CTL_198_DATA	0x0003ffff // AXI3_END_ADDR_5:RW:0:18:=0x03ffff
+#define DENALI_CTL_199_DATA	0x00000000 // AXI3_START_ADDR_6:RW:0:18:=0x000000
+#define DENALI_CTL_200_DATA	0x0003ffff // AXI3_END_ADDR_6:RW:0:18:=0x03ffff
+#define DENALI_CTL_201_DATA	0x00000000 // AXI3_START_ADDR_7:RW:0:18:=0x000000
+#define DENALI_CTL_202_DATA	0x0003ffff // AXI3_END_ADDR_7:RW:0:18:=0x03ffff
+#define DENALI_CTL_203_DATA	0x00000000 // AXI3_START_ADDR_8:RW:0:18:=0x000000
+#define DENALI_CTL_204_DATA	0x0003ffff // AXI3_END_ADDR_8:RW:0:18:=0x03ffff
+#define DENALI_CTL_205_DATA	0x00000000 // AXI3_START_ADDR_9:RW:0:18:=0x000000
+#define DENALI_CTL_206_DATA	0x0003ffff // AXI3_END_ADDR_9:RW:0:18:=0x03ffff
+#define DENALI_CTL_207_DATA	0x00000000 // AXI3_START_ADDR_10:RW:0:18:=0x000000
+#define DENALI_CTL_208_DATA	0x0003ffff // AXI3_END_ADDR_10:RW:0:18:=0x03ffff
+#define DENALI_CTL_209_DATA	0x00000000 // AXI3_START_ADDR_11:RW:0:18:=0x000000
+#define DENALI_CTL_210_DATA	0x0003ffff // AXI3_END_ADDR_11:RW:0:18:=0x03ffff
+#define DENALI_CTL_211_DATA	0x00000000 // AXI3_START_ADDR_12:RW:0:18:=0x000000
+#define DENALI_CTL_212_DATA	0x0003ffff // AXI3_END_ADDR_12:RW:0:18:=0x03ffff
+#define DENALI_CTL_213_DATA	0x00000000 // AXI3_START_ADDR_13:RW:0:18:=0x000000
+#define DENALI_CTL_214_DATA	0x0003ffff // AXI3_END_ADDR_13:RW:0:18:=0x03ffff
+#define DENALI_CTL_215_DATA	0x00000000 // AXI3_START_ADDR_14:RW:0:18:=0x000000
+#define DENALI_CTL_216_DATA	0x0003ffff // AXI3_END_ADDR_14:RW:0:18:=0x03ffff
+#define DENALI_CTL_217_DATA	0x00000000 // AXI3_START_ADDR_15:RW:0:18:=0x000000
+#define DENALI_CTL_218_DATA	0x0303ffff // AXI0_RANGE_PROT_BITS_0:RW:24:2:=0x03 AXI3_END_ADDR_15:RW:0:18:=0x03ffff
+#define DENALI_CTL_219_DATA	0xffffffff // AXI0_RANGE_WID_CHECK_BITS_0:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_0:RW:0:16:=0xffff
+#define DENALI_CTL_220_DATA	0x00030f0f // AXI0_RANGE_PROT_BITS_1:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_0:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_0:RW:0:4:=0x0f
+#define DENALI_CTL_221_DATA	0xffffffff // AXI0_RANGE_WID_CHECK_BITS_1:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_1:RW:0:16:=0xffff
+#define DENALI_CTL_222_DATA	0x00030f0f // AXI0_RANGE_PROT_BITS_2:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_1:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_1:RW:0:4:=0x0f
+#define DENALI_CTL_223_DATA	0xffffffff // AXI0_RANGE_WID_CHECK_BITS_2:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_2:RW:0:16:=0xffff
+#define DENALI_CTL_224_DATA	0x00030f0f // AXI0_RANGE_PROT_BITS_3:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_2:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_2:RW:0:4:=0x0f
+#define DENALI_CTL_225_DATA	0xffffffff // AXI0_RANGE_WID_CHECK_BITS_3:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_3:RW:0:16:=0xffff
+#define DENALI_CTL_226_DATA	0x00030f0f // AXI0_RANGE_PROT_BITS_4:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_3:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_3:RW:0:4:=0x0f
+#define DENALI_CTL_227_DATA	0xffffffff // AXI0_RANGE_WID_CHECK_BITS_4:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_4:RW:0:16:=0xffff
+#define DENALI_CTL_228_DATA	0x00030f0f // AXI0_RANGE_PROT_BITS_5:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_4:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_4:RW:0:4:=0x0f
+#define DENALI_CTL_229_DATA	0xffffffff // AXI0_RANGE_WID_CHECK_BITS_5:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_5:RW:0:16:=0xffff
+#define DENALI_CTL_230_DATA	0x00030f0f // AXI0_RANGE_PROT_BITS_6:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_5:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_5:RW:0:4:=0x0f
+#define DENALI_CTL_231_DATA	0xffffffff // AXI0_RANGE_WID_CHECK_BITS_6:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_6:RW:0:16:=0xffff
+#define DENALI_CTL_232_DATA	0x00030f0f // AXI0_RANGE_PROT_BITS_7:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_6:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_6:RW:0:4:=0x0f
+#define DENALI_CTL_233_DATA	0xffffffff // AXI0_RANGE_WID_CHECK_BITS_7:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_7:RW:0:16:=0xffff
+#define DENALI_CTL_234_DATA	0x00030f0f // AXI0_RANGE_PROT_BITS_8:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_7:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_7:RW:0:4:=0x0f
+#define DENALI_CTL_235_DATA	0xffffffff // AXI0_RANGE_WID_CHECK_BITS_8:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_8:RW:0:16:=0xffff
+#define DENALI_CTL_236_DATA	0x00030f0f // AXI0_RANGE_PROT_BITS_9:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_8:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_8:RW:0:4:=0x0f
+#define DENALI_CTL_237_DATA	0xffffffff // AXI0_RANGE_WID_CHECK_BITS_9:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_9:RW:0:16:=0xffff
+#define DENALI_CTL_238_DATA	0x00030f0f // AXI0_RANGE_PROT_BITS_10:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_9:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_9:RW:0:4:=0x0f
+#define DENALI_CTL_239_DATA	0xffffffff // AXI0_RANGE_WID_CHECK_BITS_10:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_10:RW:0:16:=0xffff
+#define DENALI_CTL_240_DATA	0x00030f0f // AXI0_RANGE_PROT_BITS_11:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_10:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_10:RW:0:4:=0x0f
+#define DENALI_CTL_241_DATA	0xffffffff // AXI0_RANGE_WID_CHECK_BITS_11:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_11:RW:0:16:=0xffff
+#define DENALI_CTL_242_DATA	0x00030f0f // AXI0_RANGE_PROT_BITS_12:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_11:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_11:RW:0:4:=0x0f
+#define DENALI_CTL_243_DATA	0xffffffff // AXI0_RANGE_WID_CHECK_BITS_12:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_12:RW:0:16:=0xffff
+#define DENALI_CTL_244_DATA	0x00030f0f // AXI0_RANGE_PROT_BITS_13:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_12:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_12:RW:0:4:=0x0f
+#define DENALI_CTL_245_DATA	0xffffffff // AXI0_RANGE_WID_CHECK_BITS_13:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_13:RW:0:16:=0xffff
+#define DENALI_CTL_246_DATA	0x00030f0f // AXI0_RANGE_PROT_BITS_14:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_13:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_13:RW:0:4:=0x0f
+#define DENALI_CTL_247_DATA	0xffffffff // AXI0_RANGE_WID_CHECK_BITS_14:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_14:RW:0:16:=0xffff
+#define DENALI_CTL_248_DATA	0x00030f0f // AXI0_RANGE_PROT_BITS_15:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_14:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_14:RW:0:4:=0x0f
+#define DENALI_CTL_249_DATA	0xffffffff // AXI0_RANGE_WID_CHECK_BITS_15:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_15:RW:0:16:=0xffff
+#define DENALI_CTL_250_DATA	0x00030f0f // AXI1_RANGE_PROT_BITS_0:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_15:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_15:RW:0:4:=0x0f
+#define DENALI_CTL_251_DATA	0xffffffff // AXI1_RANGE_WID_CHECK_BITS_0:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_0:RW:0:16:=0xffff
+#define DENALI_CTL_252_DATA	0x00030f0f // AXI1_RANGE_PROT_BITS_1:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_0:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_0:RW:0:4:=0x0f
+#define DENALI_CTL_253_DATA	0xffffffff // AXI1_RANGE_WID_CHECK_BITS_1:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_1:RW:0:16:=0xffff
+#define DENALI_CTL_254_DATA	0x00030f0f // AXI1_RANGE_PROT_BITS_2:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_1:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_1:RW:0:4:=0x0f
+#define DENALI_CTL_255_DATA	0xffffffff // AXI1_RANGE_WID_CHECK_BITS_2:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_2:RW:0:16:=0xffff
+#define DENALI_CTL_256_DATA	0x00030f0f // AXI1_RANGE_PROT_BITS_3:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_2:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_2:RW:0:4:=0x0f
+#define DENALI_CTL_257_DATA	0xffffffff // AXI1_RANGE_WID_CHECK_BITS_3:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_3:RW:0:16:=0xffff
+#define DENALI_CTL_258_DATA	0x00030f0f // AXI1_RANGE_PROT_BITS_4:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_3:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_3:RW:0:4:=0x0f
+#define DENALI_CTL_259_DATA	0xffffffff // AXI1_RANGE_WID_CHECK_BITS_4:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_4:RW:0:16:=0xffff
+#define DENALI_CTL_260_DATA	0x00030f0f // AXI1_RANGE_PROT_BITS_5:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_4:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_4:RW:0:4:=0x0f
+#define DENALI_CTL_261_DATA	0xffffffff // AXI1_RANGE_WID_CHECK_BITS_5:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_5:RW:0:16:=0xffff
+#define DENALI_CTL_262_DATA	0x00030f0f // AXI1_RANGE_PROT_BITS_6:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_5:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_5:RW:0:4:=0x0f
+#define DENALI_CTL_263_DATA	0xffffffff // AXI1_RANGE_WID_CHECK_BITS_6:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_6:RW:0:16:=0xffff
+#define DENALI_CTL_264_DATA	0x00030f0f // AXI1_RANGE_PROT_BITS_7:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_6:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_6:RW:0:4:=0x0f
+#define DENALI_CTL_265_DATA	0xffffffff // AXI1_RANGE_WID_CHECK_BITS_7:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_7:RW:0:16:=0xffff
+#define DENALI_CTL_266_DATA	0x00030f0f // AXI1_RANGE_PROT_BITS_8:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_7:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_7:RW:0:4:=0x0f
+#define DENALI_CTL_267_DATA	0xffffffff // AXI1_RANGE_WID_CHECK_BITS_8:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_8:RW:0:16:=0xffff
+#define DENALI_CTL_268_DATA	0x00030f0f // AXI1_RANGE_PROT_BITS_9:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_8:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_8:RW:0:4:=0x0f
+#define DENALI_CTL_269_DATA	0xffffffff // AXI1_RANGE_WID_CHECK_BITS_9:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_9:RW:0:16:=0xffff
+#define DENALI_CTL_270_DATA	0x00030f0f // AXI1_RANGE_PROT_BITS_10:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_9:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_9:RW:0:4:=0x0f
+#define DENALI_CTL_271_DATA	0xffffffff // AXI1_RANGE_WID_CHECK_BITS_10:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_10:RW:0:16:=0xffff
+#define DENALI_CTL_272_DATA	0x00030f0f // AXI1_RANGE_PROT_BITS_11:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_10:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_10:RW:0:4:=0x0f
+#define DENALI_CTL_273_DATA	0xffffffff // AXI1_RANGE_WID_CHECK_BITS_11:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_11:RW:0:16:=0xffff
+#define DENALI_CTL_274_DATA	0x00030f0f // AXI1_RANGE_PROT_BITS_12:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_11:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_11:RW:0:4:=0x0f
+#define DENALI_CTL_275_DATA	0xffffffff // AXI1_RANGE_WID_CHECK_BITS_12:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_12:RW:0:16:=0xffff
+#define DENALI_CTL_276_DATA	0x00030f0f // AXI1_RANGE_PROT_BITS_13:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_12:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_12:RW:0:4:=0x0f
+#define DENALI_CTL_277_DATA	0xffffffff // AXI1_RANGE_WID_CHECK_BITS_13:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_13:RW:0:16:=0xffff
+#define DENALI_CTL_278_DATA	0x00030f0f // AXI1_RANGE_PROT_BITS_14:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_13:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_13:RW:0:4:=0x0f
+#define DENALI_CTL_279_DATA	0xffffffff // AXI1_RANGE_WID_CHECK_BITS_14:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_14:RW:0:16:=0xffff
+#define DENALI_CTL_280_DATA	0x00030f0f // AXI1_RANGE_PROT_BITS_15:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_14:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_14:RW:0:4:=0x0f
+#define DENALI_CTL_281_DATA	0xffffffff // AXI1_RANGE_WID_CHECK_BITS_15:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_15:RW:0:16:=0xffff
+#define DENALI_CTL_282_DATA	0x00030f0f // AXI2_RANGE_PROT_BITS_0:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_15:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_15:RW:0:4:=0x0f
+#define DENALI_CTL_283_DATA	0xffffffff // AXI2_RANGE_WID_CHECK_BITS_0:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_0:RW:0:16:=0xffff
+#define DENALI_CTL_284_DATA	0x00030f0f // AXI2_RANGE_PROT_BITS_1:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_0:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_0:RW:0:4:=0x0f
+#define DENALI_CTL_285_DATA	0xffffffff // AXI2_RANGE_WID_CHECK_BITS_1:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_1:RW:0:16:=0xffff
+#define DENALI_CTL_286_DATA	0x00030f0f // AXI2_RANGE_PROT_BITS_2:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_1:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_1:RW:0:4:=0x0f
+#define DENALI_CTL_287_DATA	0xffffffff // AXI2_RANGE_WID_CHECK_BITS_2:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_2:RW:0:16:=0xffff
+#define DENALI_CTL_288_DATA	0x00030f0f // AXI2_RANGE_PROT_BITS_3:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_2:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_2:RW:0:4:=0x0f
+#define DENALI_CTL_289_DATA	0xffffffff // AXI2_RANGE_WID_CHECK_BITS_3:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_3:RW:0:16:=0xffff
+#define DENALI_CTL_290_DATA	0x00030f0f // AXI2_RANGE_PROT_BITS_4:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_3:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_3:RW:0:4:=0x0f
+#define DENALI_CTL_291_DATA	0xffffffff // AXI2_RANGE_WID_CHECK_BITS_4:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_4:RW:0:16:=0xffff
+#define DENALI_CTL_292_DATA	0x00030f0f // AXI2_RANGE_PROT_BITS_5:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_4:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_4:RW:0:4:=0x0f
+#define DENALI_CTL_293_DATA	0xffffffff // AXI2_RANGE_WID_CHECK_BITS_5:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_5:RW:0:16:=0xffff
+#define DENALI_CTL_294_DATA	0x00030f0f // AXI2_RANGE_PROT_BITS_6:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_5:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_5:RW:0:4:=0x0f
+#define DENALI_CTL_295_DATA	0xffffffff // AXI2_RANGE_WID_CHECK_BITS_6:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_6:RW:0:16:=0xffff
+#define DENALI_CTL_296_DATA	0x00030f0f // AXI2_RANGE_PROT_BITS_7:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_6:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_6:RW:0:4:=0x0f
+#define DENALI_CTL_297_DATA	0xffffffff // AXI2_RANGE_WID_CHECK_BITS_7:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_7:RW:0:16:=0xffff
+#define DENALI_CTL_298_DATA	0x00030f0f // AXI2_RANGE_PROT_BITS_8:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_7:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_7:RW:0:4:=0x0f
+#define DENALI_CTL_299_DATA	0xffffffff // AXI2_RANGE_WID_CHECK_BITS_8:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_8:RW:0:16:=0xffff
+#define DENALI_CTL_300_DATA	0x00030f0f // AXI2_RANGE_PROT_BITS_9:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_8:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_8:RW:0:4:=0x0f
+#define DENALI_CTL_301_DATA	0xffffffff // AXI2_RANGE_WID_CHECK_BITS_9:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_9:RW:0:16:=0xffff
+#define DENALI_CTL_302_DATA	0x00030f0f // AXI2_RANGE_PROT_BITS_10:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_9:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_9:RW:0:4:=0x0f
+#define DENALI_CTL_303_DATA	0xffffffff // AXI2_RANGE_WID_CHECK_BITS_10:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_10:RW:0:16:=0xffff
+#define DENALI_CTL_304_DATA	0x00030f0f // AXI2_RANGE_PROT_BITS_11:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_10:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_10:RW:0:4:=0x0f
+#define DENALI_CTL_305_DATA	0xffffffff // AXI2_RANGE_WID_CHECK_BITS_11:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_11:RW:0:16:=0xffff
+#define DENALI_CTL_306_DATA	0x00030f0f // AXI2_RANGE_PROT_BITS_12:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_11:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_11:RW:0:4:=0x0f
+#define DENALI_CTL_307_DATA	0xffffffff // AXI2_RANGE_WID_CHECK_BITS_12:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_12:RW:0:16:=0xffff
+#define DENALI_CTL_308_DATA	0x00030f0f // AXI2_RANGE_PROT_BITS_13:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_12:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_12:RW:0:4:=0x0f
+#define DENALI_CTL_309_DATA	0xffffffff // AXI2_RANGE_WID_CHECK_BITS_13:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_13:RW:0:16:=0xffff
+#define DENALI_CTL_310_DATA	0x00030f0f // AXI2_RANGE_PROT_BITS_14:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_13:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_13:RW:0:4:=0x0f
+#define DENALI_CTL_311_DATA	0xffffffff // AXI2_RANGE_WID_CHECK_BITS_14:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_14:RW:0:16:=0xffff
+#define DENALI_CTL_312_DATA	0x00030f0f // AXI2_RANGE_PROT_BITS_15:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_14:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_14:RW:0:4:=0x0f
+#define DENALI_CTL_313_DATA	0xffffffff // AXI2_RANGE_WID_CHECK_BITS_15:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_15:RW:0:16:=0xffff
+#define DENALI_CTL_314_DATA	0x00030f0f // AXI3_RANGE_PROT_BITS_0:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_15:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_15:RW:0:4:=0x0f
+#define DENALI_CTL_315_DATA	0xffffffff // AXI3_RANGE_WID_CHECK_BITS_0:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_0:RW:0:16:=0xffff
+#define DENALI_CTL_316_DATA	0x00030f0f // AXI3_RANGE_PROT_BITS_1:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_0:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_0:RW:0:4:=0x0f
+#define DENALI_CTL_317_DATA	0xffffffff // AXI3_RANGE_WID_CHECK_BITS_1:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_1:RW:0:16:=0xffff
+#define DENALI_CTL_318_DATA	0x00030f0f // AXI3_RANGE_PROT_BITS_2:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_1:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_1:RW:0:4:=0x0f
+#define DENALI_CTL_319_DATA	0xffffffff // AXI3_RANGE_WID_CHECK_BITS_2:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_2:RW:0:16:=0xffff
+#define DENALI_CTL_320_DATA	0x00030f0f // AXI3_RANGE_PROT_BITS_3:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_2:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_2:RW:0:4:=0x0f
+#define DENALI_CTL_321_DATA	0xffffffff // AXI3_RANGE_WID_CHECK_BITS_3:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_3:RW:0:16:=0xffff
+#define DENALI_CTL_322_DATA	0x00030f0f // AXI3_RANGE_PROT_BITS_4:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_3:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_3:RW:0:4:=0x0f
+#define DENALI_CTL_323_DATA	0xffffffff // AXI3_RANGE_WID_CHECK_BITS_4:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_4:RW:0:16:=0xffff
+#define DENALI_CTL_324_DATA	0x00030f0f // AXI3_RANGE_PROT_BITS_5:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_4:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_4:RW:0:4:=0x0f
+#define DENALI_CTL_325_DATA	0xffffffff // AXI3_RANGE_WID_CHECK_BITS_5:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_5:RW:0:16:=0xffff
+#define DENALI_CTL_326_DATA	0x00030f0f // AXI3_RANGE_PROT_BITS_6:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_5:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_5:RW:0:4:=0x0f
+#define DENALI_CTL_327_DATA	0xffffffff // AXI3_RANGE_WID_CHECK_BITS_6:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_6:RW:0:16:=0xffff
+#define DENALI_CTL_328_DATA	0x00030f0f // AXI3_RANGE_PROT_BITS_7:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_6:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_6:RW:0:4:=0x0f
+#define DENALI_CTL_329_DATA	0xffffffff // AXI3_RANGE_WID_CHECK_BITS_7:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_7:RW:0:16:=0xffff
+#define DENALI_CTL_330_DATA	0x00030f0f // AXI3_RANGE_PROT_BITS_8:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_7:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_7:RW:0:4:=0x0f
+#define DENALI_CTL_331_DATA	0xffffffff // AXI3_RANGE_WID_CHECK_BITS_8:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_8:RW:0:16:=0xffff
+#define DENALI_CTL_332_DATA	0x00030f0f // AXI3_RANGE_PROT_BITS_9:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_8:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_8:RW:0:4:=0x0f
+#define DENALI_CTL_333_DATA	0xffffffff // AXI3_RANGE_WID_CHECK_BITS_9:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_9:RW:0:16:=0xffff
+#define DENALI_CTL_334_DATA	0x00030f0f // AXI3_RANGE_PROT_BITS_10:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_9:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_9:RW:0:4:=0x0f
+#define DENALI_CTL_335_DATA	0xffffffff // AXI3_RANGE_WID_CHECK_BITS_10:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_10:RW:0:16:=0xffff
+#define DENALI_CTL_336_DATA	0x00030f0f // AXI3_RANGE_PROT_BITS_11:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_10:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_10:RW:0:4:=0x0f
+#define DENALI_CTL_337_DATA	0xffffffff // AXI3_RANGE_WID_CHECK_BITS_11:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_11:RW:0:16:=0xffff
+#define DENALI_CTL_338_DATA	0x00030f0f // AXI3_RANGE_PROT_BITS_12:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_11:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_11:RW:0:4:=0x0f
+#define DENALI_CTL_339_DATA	0xffffffff // AXI3_RANGE_WID_CHECK_BITS_12:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_12:RW:0:16:=0xffff
+#define DENALI_CTL_340_DATA	0x00030f0f // AXI3_RANGE_PROT_BITS_13:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_12:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_12:RW:0:4:=0x0f
+#define DENALI_CTL_341_DATA	0xffffffff // AXI3_RANGE_WID_CHECK_BITS_13:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_13:RW:0:16:=0xffff
+#define DENALI_CTL_342_DATA	0x00030f0f // AXI3_RANGE_PROT_BITS_14:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_13:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_13:RW:0:4:=0x0f
+#define DENALI_CTL_343_DATA	0xffffffff // AXI3_RANGE_WID_CHECK_BITS_14:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_14:RW:0:16:=0xffff
+#define DENALI_CTL_344_DATA	0x00030f0f // AXI3_RANGE_PROT_BITS_15:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_14:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_14:RW:0:4:=0x0f
+#define DENALI_CTL_345_DATA	0xffffffff // AXI3_RANGE_WID_CHECK_BITS_15:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_15:RW:0:16:=0xffff
+#define DENALI_CTL_346_DATA	0x32030f0f // AXI0_BDW:RW:24:7:=0x32 ARB_CMD_Q_THRESHOLD:RW:16:3:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_15:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_15:RW:0:4:=0x0f
+#define DENALI_CTL_347_DATA	0x01320001 // AXI1_BDW_OVFLOW:RW:24:1:=0x01 AXI1_BDW:RW:16:7:=0x32 AXI0_CURRENT_BDW:RD:8:7:=0x00 AXI0_BDW_OVFLOW:RW:0:1:=0x01
+#define DENALI_CTL_348_DATA	0x00013200 // AXI2_CURRENT_BDW:RD:24:7:=0x00 AXI2_BDW_OVFLOW:RW:16:1:=0x01 AXI2_BDW:RW:8:7:=0x32 AXI1_CURRENT_BDW:RD:0:7:=0x00
+#define DENALI_CTL_349_DATA	0x00000132 // CKE_STATUS:RD:24:2:=0x00 AXI3_CURRENT_BDW:RD:16:7:=0x00 AXI3_BDW_OVFLOW:RW:8:1:=0x01 AXI3_BDW:RW:0:7:=0x32
+#define DENALI_CTL_350_DATA	0x00000000 // DLL_RST_ADJ_DLY:RW:24:8:=0x00 DLL_RST_DELAY:RW:8:16:=0x0000 MEM_RST_VALID:RD:0:1:=0x00
+#define DENALI_CTL_351_DATA	0x000d0000 // TDFI_RDDATA_EN:RD:24:6:=0x00 TDFI_PHY_RDLAT:RW_D:16:6:=0x0d UPDATE_ERROR_STATUS:RD:8:7:=0x00 TDFI_PHY_WRLAT:RD:0:6:=0x00
+#define DENALI_CTL_352_DATA	0x1e680000 // TDFI_CTRLUPD_MAX:RW:16:14:=0x1e68 TDFI_CTRLUPD_MIN:RD:8:4:=0x00 DRAM_CLK_DISABLE:RW:0:2:=0x00
+#define DENALI_CTL_353_DATA	0x02000200 // TDFI_PHYUPD_TYPE1:RW:16:16:=0x0200 TDFI_PHYUPD_TYPE0:RW:0:16:=0x0200
+#define DENALI_CTL_354_DATA	0x02000200 // TDFI_PHYUPD_TYPE3:RW:16:16:=0x0200 TDFI_PHYUPD_TYPE2:RW:0:16:=0x0200
+#define DENALI_CTL_355_DATA	0x00001e68 // TDFI_PHYUPD_RESP:RW:0:14:=0x1e68
+#define DENALI_CTL_356_DATA	0x00009808 // TDFI_CTRLUPD_INTERVAL:RW:0:32:=0x00009808
+#define DENALI_CTL_357_DATA	0x00020608 // TDFI_DRAM_CLK_DISABLE:RW:24:4:=0x00 TDFI_CTRL_DELAY:RW_D:16:4:=0x02 WRLAT_ADJ:RW:8:6:=0x06 RDLAT_ADJ:RW:0:6:=0x08
+#define DENALI_CTL_358_DATA	0x000a0a01 // TDFI_WRLVL_WW:RW:16:10:=0x000a TDFI_WRLVL_EN:RW:8:8:=0x0a TDFI_DRAM_CLK_ENABLE:RW:0:4:=0x01
+#define DENALI_CTL_359_DATA	0x00000000 // TDFI_WRLVL_RESP:RW:0:32:=0x00000000
+#define DENALI_CTL_360_DATA	0x00000000 // TDFI_WRLVL_MAX:RW:0:32:=0x00000000
+#define DENALI_CTL_361_DATA	0x04038000 // TDFI_WRLVL_RESPLAT:RW:24:8:=0x04 TDFI_WRLVL_DLL:RW:16:8:=0x03 DFI_WRLVL_MAX_DELAY:RW:0:16:=0x8000
+#define DENALI_CTL_362_DATA	0x07030a07 // TDFI_RDLVL_LOAD:RW:24:8:=0x07 TDFI_RDLVL_DLL:RW:16:8:=0x03 TDFI_RDLVL_EN:RW:8:8:=0x0a TDFI_WRLVL_LOAD:RW:0:8:=0x07
+#define DENALI_CTL_363_DATA	0x00ffff22 // RDLVL_MAX_DELAY:RW:8:16:=0xffff TDFI_RDLVL_RESPLAT:RW:0:8:=0x22
+#define DENALI_CTL_364_DATA	0x000f0010 // TDFI_RDLVL_RR:RW:16:10:=0x000f RDLVL_GATE_MAX_DELAY:RW:0:16:=0x0010
+#define DENALI_CTL_365_DATA	0x00000000 // TDFI_RDLVL_RESP:RW:0:32:=0x00000000
+#define DENALI_CTL_366_DATA	0x00000000 // RDLVL_RESP_MASK:RW:0:20:=0x000000
+#define DENALI_CTL_367_DATA	0x00000000 // RDLVL_EN:RW:24:1:=0x00 RDLVL_GATE_RESP_MASK:RW:0:20:=0x000000
+#define DENALI_CTL_368_DATA	0x00000000 // RDLVL_GATE_PREAMBLE_CHECK_EN:RW:8:1:=0x00 RDLVL_GATE_EN:RW:0:1:=0x00
+#define DENALI_CTL_369_DATA	0x00000000 // TDFI_RDLVL_MAX:RW:0:32:=0x00000000
+#define DENALI_CTL_370_DATA	0x00000204 // RDLVL_ERROR_STATUS:RD:16:14:=0x0000 RDLVL_GATE_DQ_ZERO_COUNT:RW:8:4:=0x02 RDLVL_DQ_ZERO_COUNT:RW:0:4:=0x04
+#define DENALI_CTL_371_DATA	0x00000000 // RDLVL_GATE_INTERVAL:RW:16:16:=0x0000 RDLVL_INTERVAL:RW:0:16:=0x0000
+#define DENALI_CTL_372_DATA	0x01000001 // OPTIMAL_RMODW_EN:RW:24:1:=0x01 MEMCD_RMODW_FIFO_PTR_WIDTH:RD:16:8:=0x00 MEMCD_RMODW_FIFO_DEPTH:RD:8:8:=0x00 TDFI_PHY_WRDATA:RW:0:3:=0x01
+#define DENALI_CTL_373_DATA	0x00000001 // RESERVED:RW:24:1:=0x00 RESERVED:RW:16:5:=0x00 RESERVED:RW:8:1:=0x00 RESERVED:RW:0:1:=0x01
+#define DENALI_CTL_374_DATA	0x00000000 // AXI3_ALL_STROBES_USED_ENABLE:RW:24:1:=0x00 AXI2_ALL_STROBES_USED_ENABLE:RW:16:1:=0x00 AXI1_ALL_STROBES_USED_ENABLE:RW:8:1:=0x00 AXI0_ALL_STROBES_USED_ENABLE:RW:0:1:=0x00
+
diff --git a/include/renesas/jedec_ddr3_2g_x16_1333h_500_cl8.h b/include/renesas/jedec_ddr3_2g_x16_1333h_500_cl8.h
new file mode 100644
index 0000000000..cfef7fa0bf
--- /dev/null
+++ b/include/renesas/jedec_ddr3_2g_x16_1333h_500_cl8.h
@@ -0,0 +1,399 @@ 
+
+/* ****************************************************************
+ *        CADENCE                    Copyright (c) 2001-2011      *
+ *                                   Cadence Design Systems, Inc. *
+ *                                   All rights reserved.         *
+ *                                                                *
+ ******************************************************************
+ *  The values calculated from this script are meant to be        *
+ *  representative programmings.   The values may not reflect the *
+ *  actual required programming for production use.   Please      *
+ *  closely review all programmed values for technical accuracy   *
+ *  before use in production parts.                               *
+ ******************************************************************
+ *
+ *   Module:         regconfig.h
+ *   Documentation:  Register programming header file
+ *
+ ******************************************************************
+ ******************************************************************
+ * WARNING:  This file was automatically generated.  Manual
+ * editing may result in undetermined behavior.
+ ******************************************************************
+ ******************************************************************/
+
+#define DENALI_CTL_00_DATA	0x00000600
+#define DENALI_CTL_01_DATA	0x00000000
+#define DENALI_CTL_02_DATA	0x00000000
+#define DENALI_CTL_03_DATA	0x00000000
+#define DENALI_CTL_04_DATA	0x00000000
+#define DENALI_CTL_05_DATA	0x00000000
+#define DENALI_CTL_06_DATA	0x00000000
+#define DENALI_CTL_07_DATA	0x00000005
+#define DENALI_CTL_08_DATA	0x000186a0
+#define DENALI_CTL_09_DATA	0x0003d090
+#define DENALI_CTL_10_DATA	0x00000000
+#define DENALI_CTL_11_DATA	0x10000200
+#define DENALI_CTL_12_DATA	0x04040006
+#define DENALI_CTL_13_DATA	0x04121904
+#define DENALI_CTL_14_DATA	0x04041707
+#define DENALI_CTL_15_DATA	0x00891c0c
+#define DENALI_CTL_16_DATA	0x07000503
+#define DENALI_CTL_17_DATA	0x01010008
+#define DENALI_CTL_18_DATA	0x0007030f
+#define DENALI_CTL_19_DATA	0x01000000
+#define DENALI_CTL_20_DATA	0x0f340050
+#define DENALI_CTL_21_DATA	0x00000005
+#define DENALI_CTL_22_DATA	0x000c0003
+#define DENALI_CTL_23_DATA	0x00000000
+#define DENALI_CTL_24_DATA	0x00550200
+#define DENALI_CTL_25_DATA	0x00010000
+#define DENALI_CTL_26_DATA	0x00050500
+#define DENALI_CTL_27_DATA	0x00000000
+#define DENALI_CTL_28_DATA	0x00000000
+#define DENALI_CTL_29_DATA	0x00000000
+#define DENALI_CTL_30_DATA	0x00000000
+#define DENALI_CTL_31_DATA	0x00084000
+#define DENALI_CTL_32_DATA	0x00080046
+#define DENALI_CTL_33_DATA	0x00000000
+#define DENALI_CTL_34_DATA	0x00460840
+#define DENALI_CTL_35_DATA	0x00000008
+#define DENALI_CTL_36_DATA	0x00010000
+#define DENALI_CTL_37_DATA	0x00000000
+#define DENALI_CTL_38_DATA	0x00000000
+#define DENALI_CTL_39_DATA	0x00000000
+#define DENALI_CTL_40_DATA	0x00000000
+#define DENALI_CTL_41_DATA	0x00000000
+#define DENALI_CTL_42_DATA	0x00000000
+#define DENALI_CTL_43_DATA	0x00000000
+#define DENALI_CTL_44_DATA	0x00000000
+#define DENALI_CTL_45_DATA	0x01000200
+#define DENALI_CTL_46_DATA	0x02000040
+#define DENALI_CTL_47_DATA	0x00000040
+#define DENALI_CTL_48_DATA	0x02000100
+#define DENALI_CTL_49_DATA	0xffff0a01
+#define DENALI_CTL_50_DATA	0x01010101
+#define DENALI_CTL_51_DATA	0x01010101
+#define DENALI_CTL_52_DATA	0x01030101
+#define DENALI_CTL_53_DATA	0x0c030000
+#define DENALI_CTL_54_DATA	0x00000000
+#define DENALI_CTL_55_DATA	0x00000100
+#define DENALI_CTL_56_DATA	0x00000000
+#define DENALI_CTL_57_DATA	0x00000000
+#define DENALI_CTL_58_DATA	0x00000000
+#define DENALI_CTL_59_DATA	0x00000000
+#define DENALI_CTL_60_DATA	0x00000000
+#define DENALI_CTL_61_DATA	0x00000000
+#define DENALI_CTL_62_DATA	0x01020000
+#define DENALI_CTL_63_DATA	0x06050201
+#define DENALI_CTL_64_DATA	0x02000106
+#define DENALI_CTL_65_DATA	0x00000000
+#define DENALI_CTL_66_DATA	0x02020202
+#define DENALI_CTL_67_DATA	0x00000200
+#define DENALI_CTL_68_DATA	0x00000000
+#define DENALI_CTL_69_DATA	0x00000000
+#define DENALI_CTL_70_DATA	0x00000000
+#define DENALI_CTL_71_DATA	0x00280d00
+#define DENALI_CTL_72_DATA	0x00000000
+#define DENALI_CTL_73_DATA	0x00000100
+#define DENALI_CTL_74_DATA	0x00010001
+#define DENALI_CTL_75_DATA	0x00000000
+#define DENALI_CTL_76_DATA	0x00000000
+#define DENALI_CTL_77_DATA	0x00000000
+#define DENALI_CTL_78_DATA	0x00000000
+#define DENALI_CTL_79_DATA	0x00222200
+#define DENALI_CTL_80_DATA	0x00000001
+#define DENALI_CTL_81_DATA	0x00000000
+#define DENALI_CTL_82_DATA	0x00000000
+#define DENALI_CTL_83_DATA	0x00012222
+#define DENALI_CTL_84_DATA	0x00000000
+#define DENALI_CTL_85_DATA	0x00000000
+#define DENALI_CTL_86_DATA	0x00222200
+#define DENALI_CTL_87_DATA	0x02020001
+#define DENALI_CTL_88_DATA	0x00020200
+#define DENALI_CTL_89_DATA	0x02000202
+#define DENALI_CTL_90_DATA	0x01000002
+#define DENALI_CTL_91_DATA	0x00000000
+#define DENALI_CTL_92_DATA	0x0003ffff
+#define DENALI_CTL_93_DATA	0x00000000
+#define DENALI_CTL_94_DATA	0x0003ffff
+#define DENALI_CTL_95_DATA	0x00000000
+#define DENALI_CTL_96_DATA	0x0003ffff
+#define DENALI_CTL_97_DATA	0x00000000
+#define DENALI_CTL_98_DATA	0x0003ffff
+#define DENALI_CTL_99_DATA	0x00000000
+#define DENALI_CTL_100_DATA	0x0003ffff
+#define DENALI_CTL_101_DATA	0x00000000
+#define DENALI_CTL_102_DATA	0x0003ffff
+#define DENALI_CTL_103_DATA	0x00000000
+#define DENALI_CTL_104_DATA	0x0003ffff
+#define DENALI_CTL_105_DATA	0x00000000
+#define DENALI_CTL_106_DATA	0x0003ffff
+#define DENALI_CTL_107_DATA	0x00000000
+#define DENALI_CTL_108_DATA	0x0003ffff
+#define DENALI_CTL_109_DATA	0x00000000
+#define DENALI_CTL_110_DATA	0x0003ffff
+#define DENALI_CTL_111_DATA	0x00000000
+#define DENALI_CTL_112_DATA	0x0003ffff
+#define DENALI_CTL_113_DATA	0x00000000
+#define DENALI_CTL_114_DATA	0x0003ffff
+#define DENALI_CTL_115_DATA	0x00000000
+#define DENALI_CTL_116_DATA	0x0003ffff
+#define DENALI_CTL_117_DATA	0x00000000
+#define DENALI_CTL_118_DATA	0x0003ffff
+#define DENALI_CTL_119_DATA	0x00000000
+#define DENALI_CTL_120_DATA	0x0003ffff
+#define DENALI_CTL_121_DATA	0x00000000
+#define DENALI_CTL_122_DATA	0x0003ffff
+#define DENALI_CTL_123_DATA	0x00000000
+#define DENALI_CTL_124_DATA	0x0003ffff
+#define DENALI_CTL_125_DATA	0x00000000
+#define DENALI_CTL_126_DATA	0x0003ffff
+#define DENALI_CTL_127_DATA	0x00000000
+#define DENALI_CTL_128_DATA	0x0003ffff
+#define DENALI_CTL_129_DATA	0x00000000
+#define DENALI_CTL_130_DATA	0x0003ffff
+#define DENALI_CTL_131_DATA	0x00000000
+#define DENALI_CTL_132_DATA	0x0003ffff
+#define DENALI_CTL_133_DATA	0x00000000
+#define DENALI_CTL_134_DATA	0x0003ffff
+#define DENALI_CTL_135_DATA	0x00000000
+#define DENALI_CTL_136_DATA	0x0003ffff
+#define DENALI_CTL_137_DATA	0x00000000
+#define DENALI_CTL_138_DATA	0x0003ffff
+#define DENALI_CTL_139_DATA	0x00000000
+#define DENALI_CTL_140_DATA	0x0003ffff
+#define DENALI_CTL_141_DATA	0x00000000
+#define DENALI_CTL_142_DATA	0x0003ffff
+#define DENALI_CTL_143_DATA	0x00000000
+#define DENALI_CTL_144_DATA	0x0003ffff
+#define DENALI_CTL_145_DATA	0x00000000
+#define DENALI_CTL_146_DATA	0x0003ffff
+#define DENALI_CTL_147_DATA	0x00000000
+#define DENALI_CTL_148_DATA	0x0003ffff
+#define DENALI_CTL_149_DATA	0x00000000
+#define DENALI_CTL_150_DATA	0x0003ffff
+#define DENALI_CTL_151_DATA	0x00000000
+#define DENALI_CTL_152_DATA	0x0003ffff
+#define DENALI_CTL_153_DATA	0x00000000
+#define DENALI_CTL_154_DATA	0x0003ffff
+#define DENALI_CTL_155_DATA	0x00000000
+#define DENALI_CTL_156_DATA	0x0003ffff
+#define DENALI_CTL_157_DATA	0x00000000
+#define DENALI_CTL_158_DATA	0x0003ffff
+#define DENALI_CTL_159_DATA	0x00000000
+#define DENALI_CTL_160_DATA	0x0003ffff
+#define DENALI_CTL_161_DATA	0x00000000
+#define DENALI_CTL_162_DATA	0x0003ffff
+#define DENALI_CTL_163_DATA	0x00000000
+#define DENALI_CTL_164_DATA	0x0003ffff
+#define DENALI_CTL_165_DATA	0x00000000
+#define DENALI_CTL_166_DATA	0x0003ffff
+#define DENALI_CTL_167_DATA	0x00000000
+#define DENALI_CTL_168_DATA	0x0003ffff
+#define DENALI_CTL_169_DATA	0x00000000
+#define DENALI_CTL_170_DATA	0x0003ffff
+#define DENALI_CTL_171_DATA	0x00000000
+#define DENALI_CTL_172_DATA	0x0003ffff
+#define DENALI_CTL_173_DATA	0x00000000
+#define DENALI_CTL_174_DATA	0x0003ffff
+#define DENALI_CTL_175_DATA	0x00000000
+#define DENALI_CTL_176_DATA	0x0003ffff
+#define DENALI_CTL_177_DATA	0x00000000
+#define DENALI_CTL_178_DATA	0x0003ffff
+#define DENALI_CTL_179_DATA	0x00000000
+#define DENALI_CTL_180_DATA	0x0003ffff
+#define DENALI_CTL_181_DATA	0x00000000
+#define DENALI_CTL_182_DATA	0x0003ffff
+#define DENALI_CTL_183_DATA	0x00000000
+#define DENALI_CTL_184_DATA	0x0003ffff
+#define DENALI_CTL_185_DATA	0x00000000
+#define DENALI_CTL_186_DATA	0x0003ffff
+#define DENALI_CTL_187_DATA	0x00000000
+#define DENALI_CTL_188_DATA	0x0003ffff
+#define DENALI_CTL_189_DATA	0x00000000
+#define DENALI_CTL_190_DATA	0x0003ffff
+#define DENALI_CTL_191_DATA	0x00000000
+#define DENALI_CTL_192_DATA	0x0003ffff
+#define DENALI_CTL_193_DATA	0x00000000
+#define DENALI_CTL_194_DATA	0x0003ffff
+#define DENALI_CTL_195_DATA	0x00000000
+#define DENALI_CTL_196_DATA	0x0003ffff
+#define DENALI_CTL_197_DATA	0x00000000
+#define DENALI_CTL_198_DATA	0x0003ffff
+#define DENALI_CTL_199_DATA	0x00000000
+#define DENALI_CTL_200_DATA	0x0003ffff
+#define DENALI_CTL_201_DATA	0x00000000
+#define DENALI_CTL_202_DATA	0x0003ffff
+#define DENALI_CTL_203_DATA	0x00000000
+#define DENALI_CTL_204_DATA	0x0003ffff
+#define DENALI_CTL_205_DATA	0x00000000
+#define DENALI_CTL_206_DATA	0x0003ffff
+#define DENALI_CTL_207_DATA	0x00000000
+#define DENALI_CTL_208_DATA	0x0003ffff
+#define DENALI_CTL_209_DATA	0x00000000
+#define DENALI_CTL_210_DATA	0x0003ffff
+#define DENALI_CTL_211_DATA	0x00000000
+#define DENALI_CTL_212_DATA	0x0003ffff
+#define DENALI_CTL_213_DATA	0x00000000
+#define DENALI_CTL_214_DATA	0x0003ffff
+#define DENALI_CTL_215_DATA	0x00000000
+#define DENALI_CTL_216_DATA	0x0003ffff
+#define DENALI_CTL_217_DATA	0x00000000
+#define DENALI_CTL_218_DATA	0x0303ffff
+#define DENALI_CTL_219_DATA	0xffffffff
+#define DENALI_CTL_220_DATA	0x00030f0f
+#define DENALI_CTL_221_DATA	0xffffffff
+#define DENALI_CTL_222_DATA	0x00030f0f
+#define DENALI_CTL_223_DATA	0xffffffff
+#define DENALI_CTL_224_DATA	0x00030f0f
+#define DENALI_CTL_225_DATA	0xffffffff
+#define DENALI_CTL_226_DATA	0x00030f0f
+#define DENALI_CTL_227_DATA	0xffffffff
+#define DENALI_CTL_228_DATA	0x00030f0f
+#define DENALI_CTL_229_DATA	0xffffffff
+#define DENALI_CTL_230_DATA	0x00030f0f
+#define DENALI_CTL_231_DATA	0xffffffff
+#define DENALI_CTL_232_DATA	0x00030f0f
+#define DENALI_CTL_233_DATA	0xffffffff
+#define DENALI_CTL_234_DATA	0x00030f0f
+#define DENALI_CTL_235_DATA	0xffffffff
+#define DENALI_CTL_236_DATA	0x00030f0f
+#define DENALI_CTL_237_DATA	0xffffffff
+#define DENALI_CTL_238_DATA	0x00030f0f
+#define DENALI_CTL_239_DATA	0xffffffff
+#define DENALI_CTL_240_DATA	0x00030f0f
+#define DENALI_CTL_241_DATA	0xffffffff
+#define DENALI_CTL_242_DATA	0x00030f0f
+#define DENALI_CTL_243_DATA	0xffffffff
+#define DENALI_CTL_244_DATA	0x00030f0f
+#define DENALI_CTL_245_DATA	0xffffffff
+#define DENALI_CTL_246_DATA	0x00030f0f
+#define DENALI_CTL_247_DATA	0xffffffff
+#define DENALI_CTL_248_DATA	0x00030f0f
+#define DENALI_CTL_249_DATA	0xffffffff
+#define DENALI_CTL_250_DATA	0x00030f0f
+#define DENALI_CTL_251_DATA	0xffffffff
+#define DENALI_CTL_252_DATA	0x00030f0f
+#define DENALI_CTL_253_DATA	0xffffffff
+#define DENALI_CTL_254_DATA	0x00030f0f
+#define DENALI_CTL_255_DATA	0xffffffff
+#define DENALI_CTL_256_DATA	0x00030f0f
+#define DENALI_CTL_257_DATA	0xffffffff
+#define DENALI_CTL_258_DATA	0x00030f0f
+#define DENALI_CTL_259_DATA	0xffffffff
+#define DENALI_CTL_260_DATA	0x00030f0f
+#define DENALI_CTL_261_DATA	0xffffffff
+#define DENALI_CTL_262_DATA	0x00030f0f
+#define DENALI_CTL_263_DATA	0xffffffff
+#define DENALI_CTL_264_DATA	0x00030f0f
+#define DENALI_CTL_265_DATA	0xffffffff
+#define DENALI_CTL_266_DATA	0x00030f0f
+#define DENALI_CTL_267_DATA	0xffffffff
+#define DENALI_CTL_268_DATA	0x00030f0f
+#define DENALI_CTL_269_DATA	0xffffffff
+#define DENALI_CTL_270_DATA	0x00030f0f
+#define DENALI_CTL_271_DATA	0xffffffff
+#define DENALI_CTL_272_DATA	0x00030f0f
+#define DENALI_CTL_273_DATA	0xffffffff
+#define DENALI_CTL_274_DATA	0x00030f0f
+#define DENALI_CTL_275_DATA	0xffffffff
+#define DENALI_CTL_276_DATA	0x00030f0f
+#define DENALI_CTL_277_DATA	0xffffffff
+#define DENALI_CTL_278_DATA	0x00030f0f
+#define DENALI_CTL_279_DATA	0xffffffff
+#define DENALI_CTL_280_DATA	0x00030f0f
+#define DENALI_CTL_281_DATA	0xffffffff
+#define DENALI_CTL_282_DATA	0x00030f0f
+#define DENALI_CTL_283_DATA	0xffffffff
+#define DENALI_CTL_284_DATA	0x00030f0f
+#define DENALI_CTL_285_DATA	0xffffffff
+#define DENALI_CTL_286_DATA	0x00030f0f
+#define DENALI_CTL_287_DATA	0xffffffff
+#define DENALI_CTL_288_DATA	0x00030f0f
+#define DENALI_CTL_289_DATA	0xffffffff
+#define DENALI_CTL_290_DATA	0x00030f0f
+#define DENALI_CTL_291_DATA	0xffffffff
+#define DENALI_CTL_292_DATA	0x00030f0f
+#define DENALI_CTL_293_DATA	0xffffffff
+#define DENALI_CTL_294_DATA	0x00030f0f
+#define DENALI_CTL_295_DATA	0xffffffff
+#define DENALI_CTL_296_DATA	0x00030f0f
+#define DENALI_CTL_297_DATA	0xffffffff
+#define DENALI_CTL_298_DATA	0x00030f0f
+#define DENALI_CTL_299_DATA	0xffffffff
+#define DENALI_CTL_300_DATA	0x00030f0f
+#define DENALI_CTL_301_DATA	0xffffffff
+#define DENALI_CTL_302_DATA	0x00030f0f
+#define DENALI_CTL_303_DATA	0xffffffff
+#define DENALI_CTL_304_DATA	0x00030f0f
+#define DENALI_CTL_305_DATA	0xffffffff
+#define DENALI_CTL_306_DATA	0x00030f0f
+#define DENALI_CTL_307_DATA	0xffffffff
+#define DENALI_CTL_308_DATA	0x00030f0f
+#define DENALI_CTL_309_DATA	0xffffffff
+#define DENALI_CTL_310_DATA	0x00030f0f
+#define DENALI_CTL_311_DATA	0xffffffff
+#define DENALI_CTL_312_DATA	0x00030f0f
+#define DENALI_CTL_313_DATA	0xffffffff
+#define DENALI_CTL_314_DATA	0x00030f0f
+#define DENALI_CTL_315_DATA	0xffffffff
+#define DENALI_CTL_316_DATA	0x00030f0f
+#define DENALI_CTL_317_DATA	0xffffffff
+#define DENALI_CTL_318_DATA	0x00030f0f
+#define DENALI_CTL_319_DATA	0xffffffff
+#define DENALI_CTL_320_DATA	0x00030f0f
+#define DENALI_CTL_321_DATA	0xffffffff
+#define DENALI_CTL_322_DATA	0x00030f0f
+#define DENALI_CTL_323_DATA	0xffffffff
+#define DENALI_CTL_324_DATA	0x00030f0f
+#define DENALI_CTL_325_DATA	0xffffffff
+#define DENALI_CTL_326_DATA	0x00030f0f
+#define DENALI_CTL_327_DATA	0xffffffff
+#define DENALI_CTL_328_DATA	0x00030f0f
+#define DENALI_CTL_329_DATA	0xffffffff
+#define DENALI_CTL_330_DATA	0x00030f0f
+#define DENALI_CTL_331_DATA	0xffffffff
+#define DENALI_CTL_332_DATA	0x00030f0f
+#define DENALI_CTL_333_DATA	0xffffffff
+#define DENALI_CTL_334_DATA	0x00030f0f
+#define DENALI_CTL_335_DATA	0xffffffff
+#define DENALI_CTL_336_DATA	0x00030f0f
+#define DENALI_CTL_337_DATA	0xffffffff
+#define DENALI_CTL_338_DATA	0x00030f0f
+#define DENALI_CTL_339_DATA	0xffffffff
+#define DENALI_CTL_340_DATA	0x00030f0f
+#define DENALI_CTL_341_DATA	0xffffffff
+#define DENALI_CTL_342_DATA	0x00030f0f
+#define DENALI_CTL_343_DATA	0xffffffff
+#define DENALI_CTL_344_DATA	0x00030f0f
+#define DENALI_CTL_345_DATA	0xffffffff
+#define DENALI_CTL_346_DATA	0x32030f0f
+#define DENALI_CTL_347_DATA	0x01320001
+#define DENALI_CTL_348_DATA	0x00013200
+#define DENALI_CTL_349_DATA	0x00000132
+#define DENALI_CTL_350_DATA	0x00000000
+#define DENALI_CTL_351_DATA	0x000d0000
+#define DENALI_CTL_352_DATA	0x1e680000
+#define DENALI_CTL_353_DATA	0x02000200
+#define DENALI_CTL_354_DATA	0x02000200
+#define DENALI_CTL_355_DATA	0x00001e68
+#define DENALI_CTL_356_DATA	0x00009808
+#define DENALI_CTL_357_DATA	0x00020608
+#define DENALI_CTL_358_DATA	0x000a0a01
+#define DENALI_CTL_359_DATA	0x00000000
+#define DENALI_CTL_360_DATA	0x00000000
+#define DENALI_CTL_361_DATA	0x04038000
+#define DENALI_CTL_362_DATA	0x07030a07
+#define DENALI_CTL_363_DATA	0x00ffff22
+#define DENALI_CTL_364_DATA	0x000f0010
+#define DENALI_CTL_365_DATA	0x00000000
+#define DENALI_CTL_366_DATA	0x00000000
+#define DENALI_CTL_367_DATA	0x00000000
+#define DENALI_CTL_368_DATA	0x00000000
+#define DENALI_CTL_369_DATA	0x00000000
+#define DENALI_CTL_370_DATA	0x00000204
+#define DENALI_CTL_371_DATA	0x00000000
+#define DENALI_CTL_372_DATA	0x01000001
+#define DENALI_CTL_373_DATA	0x00000001
+#define DENALI_CTL_374_DATA	0x00000000