| Message ID | 20230501152732.9245-1-quic_tdas@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | clk: qcom: rcg: Update rcg configuration before enabling it | expand |
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 76551534f10d..b36377979f21 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -980,7 +980,13 @@ static int clk_rcg2_set_force_enable(struct clk_hw *hw) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); const char *name = clk_hw_get_name(hw); - int ret, count; + int ret, count, val; + + if (!__clk_is_enabled(hw->clk)) { + regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &val); + if (val & CMD_DIRTY_CFG) + update_config(rcg); + } ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, CMD_ROOT_EN, CMD_ROOT_EN);
If rcg is in disabled state when clk_rcg2_shared_set_rate is called, the new configuration is written to the configuration register but it won't be effective in h/w yet because update bit won't be set if rcg is in disabled state. Since the new configuration is not yet updated in h/w, dirty bit of configuration register will be set in such case. Clear the dirty bit and update the rcg to proper new configuration by setting the update bit before enabling the rcg. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> --- drivers/clk/qcom/clk-rcg2.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.17.1