| Message ID | 20230308-msm8226-mdp-v3-6-b6284145d67a@z3ntu.xyz |
|---|---|
| State | Accepted |
| Commit | 1531d0b9235e5c8e959fbfe02c90ecd5b2b8de05 |
| Headers | show |
| Series | Display support for MSM8226 | expand |
On 6/1/2023 10:00 AM, Luca Weiss wrote: > MSM8226 uses a modified PLL lock sequence compared to MSM8974, which is > based on the function dsi_pll_enable_seq_m in the msm-3.10 kernel. > > Worth noting that the msm-3.10 downstream kernel also will try other > sequences in case this one doesn't work, but during testing it has shown > that the _m sequence succeeds first time also: > > .pll_enable_seqs[0] = dsi_pll_enable_seq_m, > .pll_enable_seqs[1] = dsi_pll_enable_seq_m, > .pll_enable_seqs[2] = dsi_pll_enable_seq_d, > .pll_enable_seqs[3] = dsi_pll_enable_seq_d, > .pll_enable_seqs[4] = dsi_pll_enable_seq_f1, > .pll_enable_seqs[5] = dsi_pll_enable_seq_c, > .pll_enable_seqs[6] = dsi_pll_enable_seq_e, > > We may need to expand this in the future. > > Signed-off-by: Luca Weiss <luca@z3ntu.xyz> > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 + > drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 3 +- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 97 ++++++++++++++++++++++++++++++ > 3 files changed, 101 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > index bb09cbe8ff86..9d5795c58a98 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > @@ -541,6 +541,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { > .data = &dsi_phy_28nm_hpm_famb_cfgs }, > { .compatible = "qcom,dsi-phy-28nm-lp", > .data = &dsi_phy_28nm_lp_cfgs }, > + { .compatible = "qcom,dsi-phy-28nm-8226", > + .data = &dsi_phy_28nm_8226_cfgs }, > #endif > #ifdef CONFIG_DRM_MSM_DSI_20NM_PHY > { .compatible = "qcom,dsi-phy-20nm", > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > index 7137a17ae523..8b640d174785 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > @@ -46,8 +46,9 @@ struct msm_dsi_phy_cfg { > extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs; > -extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; > +extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8226_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs; > +extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs; > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > index 4c1bf55c5f38..ceec7bb87bf1 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > @@ -37,6 +37,7 @@ > > /* v2.0.0 28nm LP implementation */ > #define DSI_PHY_28NM_QUIRK_PHY_LP BIT(0) > +#define DSI_PHY_28NM_QUIRK_PHY_8226 BIT(1) > > #define LPFR_LUT_SIZE 10 > struct lpfr_cfg { > @@ -377,6 +378,74 @@ static int dsi_pll_28nm_vco_prepare_hpm(struct clk_hw *hw) > return ret; > } > > +static int dsi_pll_28nm_vco_prepare_8226(struct clk_hw *hw) > +{ > + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); > + struct device *dev = &pll_28nm->phy->pdev->dev; > + void __iomem *base = pll_28nm->phy->pll_base; > + u32 max_reads = 5, timeout_us = 100; > + bool locked; > + u32 val; > + int i; > + > + DBG("id=%d", pll_28nm->phy->id); > + > + pll_28nm_software_reset(pll_28nm); > + > + /* > + * PLL power up sequence. > + * Add necessary delays recommended by hardware. > + */ > + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG1, 0x34); > + > + val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; > + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); > + > + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; > + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); > + > + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; > + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; > + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); > + > + for (i = 0; i < 7; i++) { > + /* DSI Uniphy lock detect setting */ > + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); > + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, > + 0x0c, 100); > + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); > + > + /* poll for PLL ready status */ > + locked = pll_28nm_poll_for_ready(pll_28nm, > + max_reads, timeout_us); > + if (locked) > + break; > + > + pll_28nm_software_reset(pll_28nm); > + > + /* > + * PLL power up sequence. > + * Add necessary delays recommended by hardware. > + */ > + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00, 50); > + > + val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; > + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; > + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 100); > + > + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; > + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; > + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); > + } > + > + if (unlikely(!locked)) > + DRM_DEV_ERROR(dev, "DSI PLL lock failed\n"); > + else > + DBG("DSI PLL Lock success"); > + > + return locked ? 0 : -EINVAL; > +} > + Could you please share the downstream reference you used to come up with this sequence? Thanks and Regards, Jeykumar S. > static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw) > { > struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); > @@ -471,6 +540,15 @@ static const struct clk_ops clk_ops_dsi_pll_28nm_vco_lp = { > .is_enabled = dsi_pll_28nm_clk_is_enabled, > }; > > +static const struct clk_ops clk_ops_dsi_pll_28nm_vco_8226 = { > + .round_rate = dsi_pll_28nm_clk_round_rate, > + .set_rate = dsi_pll_28nm_clk_set_rate, > + .recalc_rate = dsi_pll_28nm_clk_recalc_rate, > + .prepare = dsi_pll_28nm_vco_prepare_8226, > + .unprepare = dsi_pll_28nm_vco_unprepare, > + .is_enabled = dsi_pll_28nm_clk_is_enabled, > +}; > + > /* > * PLL Callbacks > */ > @@ -536,6 +614,8 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov > > if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP) > vco_init.ops = &clk_ops_dsi_pll_28nm_vco_lp; > + else if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_8226) > + vco_init.ops = &clk_ops_dsi_pll_28nm_vco_8226; > else > vco_init.ops = &clk_ops_dsi_pll_28nm_vco_hpm; > > @@ -820,3 +900,20 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { > .quirks = DSI_PHY_28NM_QUIRK_PHY_LP, > }; > > +const struct msm_dsi_phy_cfg dsi_phy_28nm_8226_cfgs = { > + .has_phy_regulator = true, > + .regulator_data = dsi_phy_28nm_regulators, > + .num_regulators = ARRAY_SIZE(dsi_phy_28nm_regulators), > + .ops = { > + .enable = dsi_28nm_phy_enable, > + .disable = dsi_28nm_phy_disable, > + .pll_init = dsi_pll_28nm_init, > + .save_pll_state = dsi_28nm_pll_save_state, > + .restore_pll_state = dsi_28nm_pll_restore_state, > + }, > + .min_pll_rate = VCO_MIN_RATE, > + .max_pll_rate = VCO_MAX_RATE, > + .io_start = { 0xfd922b00 }, > + .num_dsi_phy = 1, > + .quirks = DSI_PHY_28NM_QUIRK_PHY_8226, > +}; >
On Mittwoch, 7. Juni 2023 21:46:31 CEST Jeykumar Sankaran wrote: > On 6/1/2023 10:00 AM, Luca Weiss wrote: > > MSM8226 uses a modified PLL lock sequence compared to MSM8974, which is > > based on the function dsi_pll_enable_seq_m in the msm-3.10 kernel. > > > > Worth noting that the msm-3.10 downstream kernel also will try other > > sequences in case this one doesn't work, but during testing it has shown > > > > that the _m sequence succeeds first time also: > > .pll_enable_seqs[0] = dsi_pll_enable_seq_m, > > .pll_enable_seqs[1] = dsi_pll_enable_seq_m, > > .pll_enable_seqs[2] = dsi_pll_enable_seq_d, > > .pll_enable_seqs[3] = dsi_pll_enable_seq_d, > > .pll_enable_seqs[4] = dsi_pll_enable_seq_f1, > > .pll_enable_seqs[5] = dsi_pll_enable_seq_c, > > .pll_enable_seqs[6] = dsi_pll_enable_seq_e, > > > > We may need to expand this in the future. > > > > Signed-off-by: Luca Weiss <luca@z3ntu.xyz> > > --- > > > > drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 + > > drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 3 +- > > drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 97 > > ++++++++++++++++++++++++++++++ 3 files changed, 101 insertions(+), 1 > > deletion(-) > > > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index bb09cbe8ff86..9d5795c58a98 > > 100644 > > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > > @@ -541,6 +541,8 @@ static const struct of_device_id dsi_phy_dt_match[] = > > { > > > > .data = &dsi_phy_28nm_hpm_famb_cfgs }, > > > > { .compatible = "qcom,dsi-phy-28nm-lp", > > > > .data = &dsi_phy_28nm_lp_cfgs }, > > > > + { .compatible = "qcom,dsi-phy-28nm-8226", > > + .data = &dsi_phy_28nm_8226_cfgs }, > > > > #endif > > #ifdef CONFIG_DRM_MSM_DSI_20NM_PHY > > > > { .compatible = "qcom,dsi-phy-20nm", > > > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 7137a17ae523..8b640d174785 > > 100644 > > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > > @@ -46,8 +46,9 @@ struct msm_dsi_phy_cfg { > > > > extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs; > > extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs; > > extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs; > > > > -extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; > > +extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8226_cfgs; > > > > extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs; > > > > +extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; > > > > extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs; > > extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs; > > extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs; > > > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index > > 4c1bf55c5f38..ceec7bb87bf1 100644 > > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > > @@ -37,6 +37,7 @@ > > > > /* v2.0.0 28nm LP implementation */ > > #define DSI_PHY_28NM_QUIRK_PHY_LP BIT(0) > > > > +#define DSI_PHY_28NM_QUIRK_PHY_8226 BIT(1) > > > > #define LPFR_LUT_SIZE 10 > > struct lpfr_cfg { > > > > @@ -377,6 +378,74 @@ static int dsi_pll_28nm_vco_prepare_hpm(struct clk_hw > > *hw)> > > return ret; > > > > } > > > > +static int dsi_pll_28nm_vco_prepare_8226(struct clk_hw *hw) > > +{ > > + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); > > + struct device *dev = &pll_28nm->phy->pdev->dev; > > + void __iomem *base = pll_28nm->phy->pll_base; > > + u32 max_reads = 5, timeout_us = 100; > > + bool locked; > > + u32 val; > > + int i; > > + > > + DBG("id=%d", pll_28nm->phy->id); > > + > > + pll_28nm_software_reset(pll_28nm); > > + > > + /* > > + * PLL power up sequence. > > + * Add necessary delays recommended by hardware. > > + */ > > + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG1, 0x34); > > + > > + val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; > > + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); > > + > > + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; > > + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); > > + > > + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; > > + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; > > + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); > > + > > + for (i = 0; i < 7; i++) { > > + /* DSI Uniphy lock detect setting */ > > + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); > > + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, > > + 0x0c, 100); > > + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); > > + > > + /* poll for PLL ready status */ > > + locked = pll_28nm_poll_for_ready(pll_28nm, > > + max_reads, timeout_us); > > + if (locked) > > + break; > > + > > + pll_28nm_software_reset(pll_28nm); > > + > > + /* > > + * PLL power up sequence. > > + * Add necessary delays recommended by hardware. > > + */ > > + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00, 50); > > + > > + val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; > > + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; > > + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 100); > > + > > + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; > > + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; > > + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); > > + } > > + > > + if (unlikely(!locked)) > > + DRM_DEV_ERROR(dev, "DSI PLL lock failed\n"); > > + else > > + DBG("DSI PLL Lock success"); > > + > > + return locked ? 0 : -EINVAL; > > +} > > + > > Could you please share the downstream reference you used to come up with > this sequence? Hi, it should be this if I don't misremember. https://android.googlesource.com/kernel/msm/+/refs/heads/android-msm-lenok-3.10-marshmallow-mr1-wear-release/arch/arm/mach-msm/clock-mdss-8974.c#1088 Regards Luca > > Thanks and Regards, > Jeykumar S. > > > static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw) > > { > > > > struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); > > > > @@ -471,6 +540,15 @@ static const struct clk_ops > > clk_ops_dsi_pll_28nm_vco_lp = {> > > .is_enabled = dsi_pll_28nm_clk_is_enabled, > > > > }; > > > > +static const struct clk_ops clk_ops_dsi_pll_28nm_vco_8226 = { > > + .round_rate = dsi_pll_28nm_clk_round_rate, > > + .set_rate = dsi_pll_28nm_clk_set_rate, > > + .recalc_rate = dsi_pll_28nm_clk_recalc_rate, > > + .prepare = dsi_pll_28nm_vco_prepare_8226, > > + .unprepare = dsi_pll_28nm_vco_unprepare, > > + .is_enabled = dsi_pll_28nm_clk_is_enabled, > > +}; > > + > > > > /* > > > > * PLL Callbacks > > */ > > > > @@ -536,6 +614,8 @@ static int pll_28nm_register(struct dsi_pll_28nm > > *pll_28nm, struct clk_hw **prov> > > if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP) > > > > vco_init.ops = &clk_ops_dsi_pll_28nm_vco_lp; > > > > + else if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_8226) > > + vco_init.ops = &clk_ops_dsi_pll_28nm_vco_8226; > > > > else > > > > vco_init.ops = &clk_ops_dsi_pll_28nm_vco_hpm; > > > > @@ -820,3 +900,20 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { > > > > .quirks = DSI_PHY_28NM_QUIRK_PHY_LP, > > > > }; > > > > +const struct msm_dsi_phy_cfg dsi_phy_28nm_8226_cfgs = { > > + .has_phy_regulator = true, > > + .regulator_data = dsi_phy_28nm_regulators, > > + .num_regulators = ARRAY_SIZE(dsi_phy_28nm_regulators), > > + .ops = { > > + .enable = dsi_28nm_phy_enable, > > + .disable = dsi_28nm_phy_disable, > > + .pll_init = dsi_pll_28nm_init, > > + .save_pll_state = dsi_28nm_pll_save_state, > > + .restore_pll_state = dsi_28nm_pll_restore_state, > > + }, > > + .min_pll_rate = VCO_MIN_RATE, > > + .max_pll_rate = VCO_MAX_RATE, > > + .io_start = { 0xfd922b00 }, > > + .num_dsi_phy = 1, > > + .quirks = DSI_PHY_28NM_QUIRK_PHY_8226, > > +};
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index bb09cbe8ff86..9d5795c58a98 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -541,6 +541,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { .data = &dsi_phy_28nm_hpm_famb_cfgs }, { .compatible = "qcom,dsi-phy-28nm-lp", .data = &dsi_phy_28nm_lp_cfgs }, + { .compatible = "qcom,dsi-phy-28nm-8226", + .data = &dsi_phy_28nm_8226_cfgs }, #endif #ifdef CONFIG_DRM_MSM_DSI_20NM_PHY { .compatible = "qcom,dsi-phy-20nm", diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 7137a17ae523..8b640d174785 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -46,8 +46,9 @@ struct msm_dsi_phy_cfg { extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs; -extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8226_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index 4c1bf55c5f38..ceec7bb87bf1 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -37,6 +37,7 @@ /* v2.0.0 28nm LP implementation */ #define DSI_PHY_28NM_QUIRK_PHY_LP BIT(0) +#define DSI_PHY_28NM_QUIRK_PHY_8226 BIT(1) #define LPFR_LUT_SIZE 10 struct lpfr_cfg { @@ -377,6 +378,74 @@ static int dsi_pll_28nm_vco_prepare_hpm(struct clk_hw *hw) return ret; } +static int dsi_pll_28nm_vco_prepare_8226(struct clk_hw *hw) +{ + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); + struct device *dev = &pll_28nm->phy->pdev->dev; + void __iomem *base = pll_28nm->phy->pll_base; + u32 max_reads = 5, timeout_us = 100; + bool locked; + u32 val; + int i; + + DBG("id=%d", pll_28nm->phy->id); + + pll_28nm_software_reset(pll_28nm); + + /* + * PLL power up sequence. + * Add necessary delays recommended by hardware. + */ + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG1, 0x34); + + val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); + + for (i = 0; i < 7; i++) { + /* DSI Uniphy lock detect setting */ + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, + 0x0c, 100); + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); + + /* poll for PLL ready status */ + locked = pll_28nm_poll_for_ready(pll_28nm, + max_reads, timeout_us); + if (locked) + break; + + pll_28nm_software_reset(pll_28nm); + + /* + * PLL power up sequence. + * Add necessary delays recommended by hardware. + */ + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00, 50); + + val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 100); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); + } + + if (unlikely(!locked)) + DRM_DEV_ERROR(dev, "DSI PLL lock failed\n"); + else + DBG("DSI PLL Lock success"); + + return locked ? 0 : -EINVAL; +} + static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); @@ -471,6 +540,15 @@ static const struct clk_ops clk_ops_dsi_pll_28nm_vco_lp = { .is_enabled = dsi_pll_28nm_clk_is_enabled, }; +static const struct clk_ops clk_ops_dsi_pll_28nm_vco_8226 = { + .round_rate = dsi_pll_28nm_clk_round_rate, + .set_rate = dsi_pll_28nm_clk_set_rate, + .recalc_rate = dsi_pll_28nm_clk_recalc_rate, + .prepare = dsi_pll_28nm_vco_prepare_8226, + .unprepare = dsi_pll_28nm_vco_unprepare, + .is_enabled = dsi_pll_28nm_clk_is_enabled, +}; + /* * PLL Callbacks */ @@ -536,6 +614,8 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP) vco_init.ops = &clk_ops_dsi_pll_28nm_vco_lp; + else if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_8226) + vco_init.ops = &clk_ops_dsi_pll_28nm_vco_8226; else vco_init.ops = &clk_ops_dsi_pll_28nm_vco_hpm; @@ -820,3 +900,20 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { .quirks = DSI_PHY_28NM_QUIRK_PHY_LP, }; +const struct msm_dsi_phy_cfg dsi_phy_28nm_8226_cfgs = { + .has_phy_regulator = true, + .regulator_data = dsi_phy_28nm_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_28nm_regulators), + .ops = { + .enable = dsi_28nm_phy_enable, + .disable = dsi_28nm_phy_disable, + .pll_init = dsi_pll_28nm_init, + .save_pll_state = dsi_28nm_pll_save_state, + .restore_pll_state = dsi_28nm_pll_restore_state, + }, + .min_pll_rate = VCO_MIN_RATE, + .max_pll_rate = VCO_MAX_RATE, + .io_start = { 0xfd922b00 }, + .num_dsi_phy = 1, + .quirks = DSI_PHY_28NM_QUIRK_PHY_8226, +};
MSM8226 uses a modified PLL lock sequence compared to MSM8974, which is based on the function dsi_pll_enable_seq_m in the msm-3.10 kernel. Worth noting that the msm-3.10 downstream kernel also will try other sequences in case this one doesn't work, but during testing it has shown that the _m sequence succeeds first time also: .pll_enable_seqs[0] = dsi_pll_enable_seq_m, .pll_enable_seqs[1] = dsi_pll_enable_seq_m, .pll_enable_seqs[2] = dsi_pll_enable_seq_d, .pll_enable_seqs[3] = dsi_pll_enable_seq_d, .pll_enable_seqs[4] = dsi_pll_enable_seq_f1, .pll_enable_seqs[5] = dsi_pll_enable_seq_c, .pll_enable_seqs[6] = dsi_pll_enable_seq_e, We may need to expand this in the future. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 3 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 97 ++++++++++++++++++++++++++++++ 3 files changed, 101 insertions(+), 1 deletion(-)