@@ -190,6 +190,8 @@ static const struct dpu_perf_cfg msm8998_perf_data = {
};
const struct dpu_mdss_cfg dpu_msm8998_cfg = {
+ .core_major_version = 0x3,
+ .core_minor_version = 0x0,
.caps = &msm8998_dpu_caps,
.ubwc = &msm8998_ubwc_cfg,
.mdp_count = ARRAY_SIZE(msm8998_mdp),
@@ -194,6 +194,8 @@ static const struct dpu_perf_cfg sdm845_perf_data = {
};
const struct dpu_mdss_cfg dpu_sdm845_cfg = {
+ .core_major_version = 0x4,
+ .core_minor_version = 0x0,
.caps = &sdm845_dpu_caps,
.ubwc = &sdm845_ubwc_cfg,
.mdp_count = ARRAY_SIZE(sdm845_mdp),
@@ -208,6 +208,8 @@ static const struct dpu_perf_cfg sm8150_perf_data = {
};
const struct dpu_mdss_cfg dpu_sm8150_cfg = {
+ .core_major_version = 0x5,
+ .core_minor_version = 0x0,
.caps = &sm8150_dpu_caps,
.ubwc = &sm8150_ubwc_cfg,
.mdp_count = ARRAY_SIZE(sm8150_mdp),
@@ -214,6 +214,8 @@ static const struct dpu_perf_cfg sc8180x_perf_data = {
};
const struct dpu_mdss_cfg dpu_sc8180x_cfg = {
+ .core_major_version = 0x5,
+ .core_minor_version = 0x1,
.caps = &sc8180x_dpu_caps,
.ubwc = &sc8180x_ubwc_cfg,
.mdp_count = ARRAY_SIZE(sc8180x_mdp),
@@ -214,6 +214,8 @@ static const struct dpu_perf_cfg sm8250_perf_data = {
};
const struct dpu_mdss_cfg dpu_sm8250_cfg = {
+ .core_major_version = 0x6,
+ .core_minor_version = 0x0,
.caps = &sm8250_dpu_caps,
.ubwc = &sm8250_ubwc_cfg,
.mdp_count = ARRAY_SIZE(sm8250_mdp),
@@ -132,6 +132,8 @@ static const struct dpu_perf_cfg sc7180_perf_data = {
};
const struct dpu_mdss_cfg dpu_sc7180_cfg = {
+ .core_major_version = 0x6,
+ .core_minor_version = 0x2,
.caps = &sc7180_dpu_caps,
.ubwc = &sc7180_ubwc_cfg,
.mdp_count = ARRAY_SIZE(sc7180_mdp),
@@ -102,6 +102,8 @@ static const struct dpu_perf_cfg sm6115_perf_data = {
};
const struct dpu_mdss_cfg dpu_sm6115_cfg = {
+ .core_major_version = 0x6,
+ .core_minor_version = 0x3,
.caps = &sm6115_dpu_caps,
.ubwc = &sm6115_ubwc_cfg,
.mdp_count = ARRAY_SIZE(sm6115_mdp),
@@ -141,6 +141,8 @@ static const struct dpu_perf_cfg sm6350_perf_data = {
};
const struct dpu_mdss_cfg dpu_sm6350_cfg = {
+ .core_major_version = 0x6,
+ .core_minor_version = 0x4,
.caps = &sm6350_dpu_caps,
.ubwc = &sm6350_ubwc_cfg,
.mdp_count = ARRAY_SIZE(sm6350_mdp),
@@ -92,6 +92,8 @@ static const struct dpu_perf_cfg qcm2290_perf_data = {
};
const struct dpu_mdss_cfg dpu_qcm2290_cfg = {
+ .core_major_version = 0x6,
+ .core_minor_version = 0x5,
.caps = &qcm2290_dpu_caps,
.ubwc = &qcm2290_ubwc_cfg,
.mdp_count = ARRAY_SIZE(qcm2290_mdp),
@@ -107,6 +107,8 @@ static const struct dpu_perf_cfg sm6375_perf_data = {
};
const struct dpu_mdss_cfg dpu_sm6375_cfg = {
+ .core_major_version = 0x6,
+ .core_minor_version = 0x9,
.caps = &sm6375_dpu_caps,
.ubwc = &sm6375_ubwc_cfg,
.mdp_count = ARRAY_SIZE(sm6375_mdp),
@@ -213,6 +213,8 @@ static const struct dpu_perf_cfg sm8350_perf_data = {
};
const struct dpu_mdss_cfg dpu_sm8350_cfg = {
+ .core_major_version = 0x7,
+ .core_minor_version = 0x0,
.caps = &sm8350_dpu_caps,
.ubwc = &sm8350_ubwc_cfg,
.mdp_count = ARRAY_SIZE(sm8350_mdp),
@@ -154,6 +154,8 @@ static const struct dpu_perf_cfg sc7280_perf_data = {
};
const struct dpu_mdss_cfg dpu_sc7280_cfg = {
+ .core_major_version = 0x7,
+ .core_minor_version = 0x2,
.caps = &sc7280_dpu_caps,
.ubwc = &sc7280_ubwc_cfg,
.mdp_count = ARRAY_SIZE(sc7280_mdp),
@@ -217,6 +217,8 @@ static const struct dpu_perf_cfg sc8280xp_perf_data = {
};
const struct dpu_mdss_cfg dpu_sc8280xp_cfg = {
+ .core_major_version = 0x8,
+ .core_minor_version = 0x0,
.caps = &sc8280xp_dpu_caps,
.ubwc = &sc8280xp_ubwc_cfg,
.mdp_count = ARRAY_SIZE(sc8280xp_mdp),
@@ -221,6 +221,8 @@ static const struct dpu_perf_cfg sm8450_perf_data = {
};
const struct dpu_mdss_cfg dpu_sm8450_cfg = {
+ .core_major_version = 0x8,
+ .core_minor_version = 0x1,
.caps = &sm8450_dpu_caps,
.ubwc = &sm8450_ubwc_cfg,
.mdp_count = ARRAY_SIZE(sm8450_mdp),
@@ -225,6 +225,8 @@ static const struct dpu_perf_cfg sm8550_perf_data = {
};
const struct dpu_mdss_cfg dpu_sm8550_cfg = {
+ .core_major_version = 0x9,
+ .core_minor_version = 0x0,
.caps = &sm8550_dpu_caps,
.ubwc = &sm8550_ubwc_cfg,
.mdp_count = ARRAY_SIZE(sm8550_mdp),
@@ -796,8 +796,9 @@ struct dpu_perf_cfg {
/**
* struct dpu_mdss_cfg - information of MDSS HW
* This is the main catalog data structure representing
- * this HW version. Contains number of instances,
- * register offsets, capabilities of the all MDSS HW sub-blocks.
+ * this HW version. Contains dpu's major and minor versions,
+ * number of instances, register offsets, capabilities of the
+ * all MDSS HW sub-blocks.
*
* @dma_formats Supported formats for dma pipe
* @cursor_formats Supported formats for cursor pipe
@@ -805,6 +806,9 @@ struct dpu_perf_cfg {
* @mdss_irqs: Bitmap with the irqs supported by the target
*/
struct dpu_mdss_cfg {
+ u8 core_major_version;
+ u8 core_minor_version;
+
const struct dpu_caps *caps;
const struct dpu_ubwc_cfg *ubwc;
With [1] dpu core revision was dropped in favor of using the compatible string from the device tree to select the dpu catalog being used in the device. This approach works well however also necessitates adding catalog entries for small register level details as dpu capabilities and/or features bloating the catalog unnecessarily. Examples include but are not limited to data_compress, interrupt register set, widebus etc. Introduce the dpu core revision back as an entry to the catalog so that we can just use dpu revision checks and enable those bits which should be enabled unconditionally and not controlled by a catalog and also simplify the changes to do something like: if (dpu_core_revision > xxxxx && dpu_core_revision < xxxxx) enable the bit; Also, add some of the useful macros back to be able to use dpu core revision effectively. [1]: https://patchwork.freedesktop.org/patch/530891/?series=113910&rev=4 changes in v2: - drop DPU step version as features are not changing across steps - add core_major_version / core_minor_version to avoid conflicts Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 8 ++++++-- 16 files changed, 36 insertions(+), 2 deletions(-)