diff mbox series

[v2,1/2] media: dt-bindings: Add binding doc for i.MX93 MIPI CSI-2

Message ID 20230710060352.584286-2-guoniu.zhou@oss.nxp.com
State New
Headers show
Series [v2,1/2] media: dt-bindings: Add binding doc for i.MX93 MIPI CSI-2 | expand

Commit Message

G.N. Zhou (OSS) July 10, 2023, 6:03 a.m. UTC 
From: "Guoniu.zhou" <guoniu.zhou@nxp.com>

Add new binding documentation for DesignWare Core MIPI CSI-2 receiver
and DPHY found on NXP i.MX93.

Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
---
 .../bindings/media/nxp,dwc-mipi-csi2.yaml     | 130 ++++++++++++++++++
 1 file changed, 130 insertions(+)

Comments

Laurent Pinchart Sept. 17, 2023, 8:46 p.m. UTC | #1 
Hello Guoniu,

Thank you for the patch.

On Mon, Jul 10, 2023 at 02:03:51PM +0800, guoniu.zhou@oss.nxp.com wrote:
> From: "Guoniu.zhou" <guoniu.zhou@nxp.com>
> 
> Add new binding documentation for DesignWare Core MIPI CSI-2 receiver
> and DPHY found on NXP i.MX93.
> 
> Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
> ---
>  .../bindings/media/nxp,dwc-mipi-csi2.yaml     | 130 ++++++++++++++++++
>  1 file changed, 130 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/media/nxp,dwc-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,dwc-mipi-csi2.yaml
> new file mode 100644
> index 000000000000..aa5d79ada9b9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/nxp,dwc-mipi-csi2.yaml
> @@ -0,0 +1,130 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/nxp,dwc-mipi-csi2.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP i.MX93 MIPI CSI-2 Host Controller receiver
> +
> +maintainers:
> +  - G.N. Zhou <guoniu.zhou@nxp.com>
> +
> +description: |-
> +  The MIPI CSI-2 receiver found on i.MX93 originates from Synopsys
> +  DesignWare Core and it implements the CSI-2 protocol on the host
> +  side and a DPHY configured as a Slave acts as the physical layer.
> +  Two data lanes are supported on i.MX93 family devices and the data
> +  rate of each lane support up to 1.5Gbps.
> +
> +  While the CSI-2 receiver is separate from the MIPI D-PHY IP core,
> +  the PHY is completely wrapped by the CSI-2 controller and expose
> +  a control interface which only can communicate with CSI-2 controller
> +  This binding thus covers both IP cores.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - fsl,imx93-mipi-csi2

Given that this is a Synopsys IP, would it make sense to have a generic
compatible string ? Something along the lines of

  compatible:
    items:
      - enum:
          - fsl,imx93-mipi-csi2
      - const: snps,dw-mipi-csi2

> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: The peripheral clock (a.k.a. APB clock)
> +      - description: The pixel clock
> +      - description: The MIPI D-PHY clock

I'm surprised that the D-PHY needs an input clock other than the one
provided by the CSI-2 clock lane. The nxp,imx-mipi-csi2.yaml binding
also requires a MIPI D-PHY clock, and I've been told some time ago that
this was actually a mistake, and that the clock was needed for the DSI
D-PHY only, not the CSI-2 D-PHY. Could you double-check this ?

> +
> +  clock-names:
> +    items:
> +      - const: per
> +      - const: pixel
> +      - const: phy_cfg
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  ports:
> +    $ref: /schemas/graph.yaml#/properties/ports
> +
> +    properties:
> +      port@0:
> +        $ref: /schemas/graph.yaml#/$defs/port-base
> +        unevaluatedProperties: false
> +        description:
> +          Input port node, single endpoint describing the CSI-2 transmitter.
> +
> +        properties:
> +          endpoint:
> +            $ref: video-interfaces.yaml#
> +            unevaluatedProperties: false
> +
> +            properties:
> +              data-lanes:
> +                minItems: 1
> +                items:
> +                  - const: 1
> +                  - const: 2
> +
> +            required:
> +              - data-lanes
> +
> +      port@1:
> +        $ref: /schemas/graph.yaml#/properties/port
> +        description:
> +          Output port node
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +  - clock-names
> +  - power-domains
> +  - ports
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/imx93-clock.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +    #include <dt-bindings/power/fsl,imx93-power.h>
> +
> +    mipi-csi@4ae00000 {
> +        compatible = "fsl,imx93-mipi-csi2";
> +        reg = <0x4ae00000 0x10000>;
> +        interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
> +        clocks = <&clks IMX93_CLK_MIPI_CSI_GATE>,
> +                 <&clks IMX93_CLK_CAM_PIX>,
> +                 <&clks IMX93_CLK_MIPI_PHY_CFG>;
> +        clock-names = "per", "pixel", "phy_cfg";
> +        power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_CSI>;
> +
> +        ports {
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +
> +            port@0 {
> +                reg = <0>;
> +
> +                mipi_from_sensor: endpoint {
> +                    remote-endpoint = <&ap1302_to_mipi>;
> +                    data-lanes = <1 2>;
> +                };
> +            };
> +
> +            port@1 {
> +                reg = <1>;
> +
> +                mipi_to_isi: endpoint {
> +                    remote-endpoint = <&isi_in>;
> +                };
> +            };
> +        };
> +    };
> +...
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/media/nxp,dwc-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,dwc-mipi-csi2.yaml
new file mode 100644
index 000000000000..aa5d79ada9b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/nxp,dwc-mipi-csi2.yaml
@@ -0,0 +1,130 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/nxp,dwc-mipi-csi2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX93 MIPI CSI-2 Host Controller receiver
+
+maintainers:
+  - G.N. Zhou <guoniu.zhou@nxp.com>
+
+description: |-
+  The MIPI CSI-2 receiver found on i.MX93 originates from Synopsys
+  DesignWare Core and it implements the CSI-2 protocol on the host
+  side and a DPHY configured as a Slave acts as the physical layer.
+  Two data lanes are supported on i.MX93 family devices and the data
+  rate of each lane support up to 1.5Gbps.
+
+  While the CSI-2 receiver is separate from the MIPI D-PHY IP core,
+  the PHY is completely wrapped by the CSI-2 controller and expose
+  a control interface which only can communicate with CSI-2 controller
+  This binding thus covers both IP cores.
+
+properties:
+  compatible:
+    enum:
+      - fsl,imx93-mipi-csi2
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: The peripheral clock (a.k.a. APB clock)
+      - description: The pixel clock
+      - description: The MIPI D-PHY clock
+
+  clock-names:
+    items:
+      - const: per
+      - const: pixel
+      - const: phy_cfg
+
+  power-domains:
+    maxItems: 1
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
+        description:
+          Input port node, single endpoint describing the CSI-2 transmitter.
+
+        properties:
+          endpoint:
+            $ref: video-interfaces.yaml#
+            unevaluatedProperties: false
+
+            properties:
+              data-lanes:
+                minItems: 1
+                items:
+                  - const: 1
+                  - const: 2
+
+            required:
+              - data-lanes
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          Output port node
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - power-domains
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx93-clock.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/power/fsl,imx93-power.h>
+
+    mipi-csi@4ae00000 {
+        compatible = "fsl,imx93-mipi-csi2";
+        reg = <0x4ae00000 0x10000>;
+        interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clks IMX93_CLK_MIPI_CSI_GATE>,
+                 <&clks IMX93_CLK_CAM_PIX>,
+                 <&clks IMX93_CLK_MIPI_PHY_CFG>;
+        clock-names = "per", "pixel", "phy_cfg";
+        power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_CSI>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+
+                mipi_from_sensor: endpoint {
+                    remote-endpoint = <&ap1302_to_mipi>;
+                    data-lanes = <1 2>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+
+                mipi_to_isi: endpoint {
+                    remote-endpoint = <&isi_in>;
+                };
+            };
+        };
+    };
+...