| Message ID | 1466601669-25398-7-git-send-email-julien.grall@arm.com |
|---|---|
| State | Superseded |
| Headers | show |
Hi Stefano, On 14/07/16 15:34, Stefano Stabellini wrote: > On Wed, 22 Jun 2016, Julien Grall wrote: >> Currently, Xen is reading the MIDR everytime it has to check whether >> the processor is affected by the erratum 766422. >> >> This could take advantage of the new capability bitfields to detect >> whether the processor is affected at boot time. >> >> With this patch, the number of instructions to check the erratum is >> going down from ~13 (including 2 loads and a co-processor access) to >> ~6 instructions (include 1 load). > > The patch looks good but the midr bits were actually already stored in > cpu_data. See: > > >> -/* Erratum 766422: only Cortex A15 r0p4 is affected */ >> -#define cpu_has_erratum_766422() \ >> - (unlikely(current_cpu_data.midr.bits == 0x410fc0f4)) > > We weren't really accessing MIDR every time. Am I missing something? The wording in the commit message is not clear. By "accessing the MDIR every time" I meant that the stored MIDR is checked every single time. current_cpu_data turns into a complex series of assembly instructions to get the data of the current CPU which involves 2 loads. I will rewrite the commit message in the next version. Cheers,
diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index 3ac97b3..748e02e 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -17,6 +17,12 @@ is_affected_midr_range(const struct arm_cpu_capabilities *entry) } static const struct arm_cpu_capabilities arm_errata[] = { + { + /* Cortex-A15 r0p4 */ + .desc = "ARM erratum 766422", + .capability = ARM32_WORKAROUND_766422, + MIDR_RANGE(MIDR_CORTEX_A15, 0x04, 0x04), + }, #if defined(CONFIG_ARM64_ERRATUM_827319) || \ defined(CONFIG_ARM64_ERRATUM_824069) { diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 8a3fac0..785e3e9 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -47,6 +47,7 @@ #include "vtimer.h" #include <asm/gic.h> #include <asm/vgic.h> +#include <asm/cpuerrata.h> /* The base of the stack must always be double-word aligned, which means * that both the kernel half of struct cpu_user_regs (which is pushed in @@ -2482,7 +2483,7 @@ static void do_trap_data_abort_guest(struct cpu_user_regs *regs, * Erratum 766422: Thumb store translation fault to Hypervisor may * not have correct HSR Rt value. */ - if ( cpu_has_erratum_766422() && (regs->cpsr & PSR_THUMB) && dabt.write ) + if ( check_workaround_766422() && (regs->cpsr & PSR_THUMB) && dabt.write ) { rc = decode_instruction(regs, &info.dabt); if ( rc ) diff --git a/xen/include/asm-arm/arm32/processor.h b/xen/include/asm-arm/arm32/processor.h index f41644d..11366bb 100644 --- a/xen/include/asm-arm/arm32/processor.h +++ b/xen/include/asm-arm/arm32/processor.h @@ -115,10 +115,6 @@ struct cpu_user_regs #define READ_SYSREG(R...) READ_SYSREG32(R) #define WRITE_SYSREG(V, R...) WRITE_SYSREG32(V, R) -/* Erratum 766422: only Cortex A15 r0p4 is affected */ -#define cpu_has_erratum_766422() \ - (unlikely(current_cpu_data.midr.bits == 0x410fc0f4)) - #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARM_ARM32_PROCESSOR_H */ diff --git a/xen/include/asm-arm/arm64/processor.h b/xen/include/asm-arm/arm64/processor.h index fef35a5..b0726ff 100644 --- a/xen/include/asm-arm/arm64/processor.h +++ b/xen/include/asm-arm/arm64/processor.h @@ -111,8 +111,6 @@ struct cpu_user_regs #define READ_SYSREG(name) READ_SYSREG64(name) #define WRITE_SYSREG(v, name) WRITE_SYSREG64(v, name) -#define cpu_has_erratum_766422() 0 - #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARM_ARM64_PROCESSOR_H */ diff --git a/xen/include/asm-arm/cpuerrata.h b/xen/include/asm-arm/cpuerrata.h index b9d8dfc..aaf3edd 100644 --- a/xen/include/asm-arm/cpuerrata.h +++ b/xen/include/asm-arm/cpuerrata.h @@ -40,6 +40,8 @@ static inline bool_t check_workaround_##erratum(void) \ #endif +CHECK_WORKAROUND_HELPER(766422, ARM32_WORKAROUND_766422, CONFIG_ARM_32) + #undef CHECK_WORKAROUND_HELPER #endif /* __ARM_CPUERRATA_H */ diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h index 78e2263..ac6eaf0 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -37,8 +37,9 @@ #define ARM64_WORKAROUND_CLEAN_CACHE 0 #define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE 1 +#define ARM32_WORKAROUND_766422 2 -#define ARM_NCAPS 2 +#define ARM_NCAPS 3 #ifndef __ASSEMBLY__ diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 1708253..15bf890 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -46,9 +46,11 @@ #define ARM_CPU_IMP_ARM 0x41 +#define ARM_CPU_PART_CORTEX_A15 0xC0F #define ARM_CPU_PART_CORTEX_A53 0xD03 #define ARM_CPU_PART_CORTEX_A57 0xD07 +#define MIDR_CORTEX_A15 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A15) #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
Currently, Xen is reading the MIDR everytime it has to check whether the processor is affected by the erratum 766422. This could take advantage of the new capability bitfields to detect whether the processor is affected at boot time. With this patch, the number of instructions to check the erratum is going down from ~13 (including 2 loads and a co-processor access) to ~6 instructions (include 1 load). Signed-off-by: Julien Grall <julien.grall@arm.com> --- xen/arch/arm/cpuerrata.c | 6 ++++++ xen/arch/arm/traps.c | 3 ++- xen/include/asm-arm/arm32/processor.h | 4 ---- xen/include/asm-arm/arm64/processor.h | 2 -- xen/include/asm-arm/cpuerrata.h | 2 ++ xen/include/asm-arm/cpufeature.h | 3 ++- xen/include/asm-arm/processor.h | 2 ++ 7 files changed, 14 insertions(+), 8 deletions(-)