| Message ID | 1468913859-30442-1-git-send-email-haojian.zhuang@linaro.org |
|---|---|
| State | New |
| Headers | show |
Hi Feng,
I think the main difference is who to handle the CRC bits. In the
designware emmc/sd controller, the whole 128-bit value is loaded into
the four response registers. There's no any shift on the 128-bit value
to remove CRC. (Refer to: drivers/mmc/host/dw_mmc.c).
In the eMMC spec, it only mentions R2 response in table.
Bit position [127:1]
Width (bits) 127
Value x
Description CID or CSD register incl.
internal CRC7
It also doesn't mention that we need to shift response value for CSD
register.
So I did this fixing patch. I think that shifting isn't common to
support all eMMC/SD controller IP. Without this patch, the eMMC stack
will only get shifted CSD register value.
It results in parse error.
Best Regards
Haojian
在 07/20/2016 04:14 PM, Tian, Feng 写道:
> Correct my words,
>
> According to SD host controller spec, the CRC field is ignored by h/c. user could only get the data between bit8 and bit127.
>
> Kind of Response | Meaning of Response | ResponseField | ResponseRegister
> ------------------------------------------------------------------------------------------------------------------------------
> R2 (CID, CSD register) | CID or CSD reg. incl. | R [127:8] | REP [119:0]
>
> So I don't think your fix is correct. Please correct me if I misunderstand.
>
> Thanks
> Feng
>
> -----Original Message-----
> From: Tian, Feng
> Sent: Wednesday, July 20, 2016 10:13 AM
> To: Haojian Zhuang <haojian.zhuang@linaro.org>
> Cc: edk2-devel@lists.01.org; guodong.xu@linaro.org; leif.lindholm@linaro.org; ard.biesheuvel@linaro.org; Tian, Feng <feng.tian@intel.com>
> Subject: RE: [edk2] [PATCH] EmmcBlockIo: fix to get CSD data
>
> Hi, Haojian
>
> Why I didn't get the lowest byte data is because it's CRC field. I thought nobody will care about it. My assumption is incorrect for your usage model?
>
> Thanks
> Feng
>
> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Haojian Zhuang
> Sent: Tuesday, July 19, 2016 3:38 PM
> To: Tian, Feng <feng.tian@intel.com>
> Cc: Haojian Zhuang <haojian.zhuang@linaro.org>; edk2-devel@lists.01.org; guodong.xu@linaro.org; leif.lindholm@linaro.org; ard.biesheuvel@linaro.org
> Subject: [edk2] [PATCH] EmmcBlockIo: fix to get CSD data
>
> The CSD structure is a 128-bit structure. But EmmcGetCsd() only loads
> 120 bits with 8-bit offset. Now fix it.
>
> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
> ---
> MdeModulePkg/Bus/Sd/EmmcDxe/EmmcBlockIo.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/MdeModulePkg/Bus/Sd/EmmcDxe/EmmcBlockIo.c b/MdeModulePkg/Bus/Sd/EmmcDxe/EmmcBlockIo.c
> index fc705e1..fe85627 100644
> --- a/MdeModulePkg/Bus/Sd/EmmcDxe/EmmcBlockIo.c
> +++ b/MdeModulePkg/Bus/Sd/EmmcDxe/EmmcBlockIo.c
> @@ -191,9 +191,9 @@ EmmcGetCsd (
> Status = PassThru->PassThru (PassThru, Device->Slot, &Packet, NULL);
> if (!EFI_ERROR (Status)) {
> //
> - // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.
> + // Copy 128bit data for CSD structure.
> //
> - CopyMem (((UINT8*)Csd) + 1, &SdMmcStatusBlk.Resp0, sizeof (EMMC_CSD) - 1);
> + CopyMem ((VOID*)Csd, &SdMmcStatusBlk.Resp0, sizeof (EMMC_CSD));
> }
>
> return Status;
>
在 07/21/2016 09:51 AM, Haojian Zhuang 写道: > Hi Feng, > > I think the main difference is who to handle the CRC bits. In the > designware emmc/sd controller, the whole 128-bit value is loaded into > the four response registers. There's no any shift on the 128-bit value > to remove CRC. (Refer to: drivers/mmc/host/dw_mmc.c). I mean the implementation in linux. $Linux/drivers/mmc/host/dw_mmc.c > > In the eMMC spec, it only mentions R2 response in table. > > Bit position [127:1] > Width (bits) 127 > Value x > Description CID or CSD register incl. > internal CRC7 > It also doesn't mention that we need to shift response value for CSD > register. > > So I did this fixing patch. I think that shifting isn't common to > support all eMMC/SD controller IP. Without this patch, the eMMC stack > will only get shifted CSD register value. > It results in parse error. > > Best Regards > Haojian > > 在 07/20/2016 04:14 PM, Tian, Feng 写道: >> Correct my words, >> >> According to SD host controller spec, the CRC field is ignored by >> h/c. user could only get the data between bit8 and bit127. >> >> Kind of Response | Meaning of Response | >> ResponseField | ResponseRegister >> ------------------------------------------------------------------------------------------------------------------------------ >> >> R2 (CID, CSD register) | CID or CSD reg. incl. | R >> [127:8] | REP [119:0] >> >> So I don't think your fix is correct. Please correct me if I >> misunderstand. >> >> Thanks >> Feng >> >> -----Original Message----- >> From: Tian, Feng >> Sent: Wednesday, July 20, 2016 10:13 AM >> To: Haojian Zhuang <haojian.zhuang@linaro.org> >> Cc: edk2-devel@lists.01.org; guodong.xu@linaro.org; >> leif.lindholm@linaro.org; ard.biesheuvel@linaro.org; Tian, Feng >> <feng.tian@intel.com> >> Subject: RE: [edk2] [PATCH] EmmcBlockIo: fix to get CSD data >> >> Hi, Haojian >> >> Why I didn't get the lowest byte data is because it's CRC field. I >> thought nobody will care about it. My assumption is incorrect for your >> usage model? >> >> Thanks >> Feng >> >> -----Original Message----- >> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of >> Haojian Zhuang >> Sent: Tuesday, July 19, 2016 3:38 PM >> To: Tian, Feng <feng.tian@intel.com> >> Cc: Haojian Zhuang <haojian.zhuang@linaro.org>; >> edk2-devel@lists.01.org; guodong.xu@linaro.org; >> leif.lindholm@linaro.org; ard.biesheuvel@linaro.org >> Subject: [edk2] [PATCH] EmmcBlockIo: fix to get CSD data >> >> The CSD structure is a 128-bit structure. But EmmcGetCsd() only loads >> 120 bits with 8-bit offset. Now fix it. >> >> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> >> --- >> MdeModulePkg/Bus/Sd/EmmcDxe/EmmcBlockIo.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/MdeModulePkg/Bus/Sd/EmmcDxe/EmmcBlockIo.c >> b/MdeModulePkg/Bus/Sd/EmmcDxe/EmmcBlockIo.c >> index fc705e1..fe85627 100644 >> --- a/MdeModulePkg/Bus/Sd/EmmcDxe/EmmcBlockIo.c >> +++ b/MdeModulePkg/Bus/Sd/EmmcDxe/EmmcBlockIo.c >> @@ -191,9 +191,9 @@ EmmcGetCsd ( >> Status = PassThru->PassThru (PassThru, Device->Slot, &Packet, NULL); >> if (!EFI_ERROR (Status)) { >> // >> - // For details, refer to SD Host Controller Simplified Spec 3.0 >> Table 2-12. >> + // Copy 128bit data for CSD structure. >> // >> - CopyMem (((UINT8*)Csd) + 1, &SdMmcStatusBlk.Resp0, sizeof >> (EMMC_CSD) - 1); >> + CopyMem ((VOID*)Csd, &SdMmcStatusBlk.Resp0, sizeof (EMMC_CSD)); >> } >> >> return Status; >>
On 2016/7/21 9:52, Haojian Zhuang wrote: > > > 在 07/21/2016 09:51 AM, Haojian Zhuang 写道: >> Hi Feng, >> >> I think the main difference is who to handle the CRC bits. In the >> designware emmc/sd controller, the whole 128-bit value is loaded into >> the four response registers. There's no any shift on the 128-bit value >> to remove CRC. (Refer to: drivers/mmc/host/dw_mmc.c). > > I mean the implementation in linux. $Linux/drivers/mmc/host/dw_mmc.c > >> >> In the eMMC spec, it only mentions R2 response in table. >> >> Bit position [127:1] >> Width (bits) 127 >> Value x >> Description CID or CSD register incl. >> internal CRC7 >> It also doesn't mention that we need to shift response value for CSD >> register. >> >> So I did this fixing patch. I think that shifting isn't common to >> support all eMMC/SD controller IP. Without this patch, the eMMC stack >> will only get shifted CSD register value. >> It results in parse error. As I checked the SDHC driver in linux, there's the same logic as you implemented in EmmcDxe. Now the question is whether EmmcDxe is designed for common code of all vendor's IP. If so, we need to provide a GetCsd() callback to handle different implementations for different vendor. Do you mind that I append the GetCsd() callback in EFI_SD_MMC_PASS_THRU_PROTOCOL to fix this issue? Best Regards Haojian
On 21 July 2016 at 13:17, Haojian Zhuang <haojian.zhuang@linaro.org> wrote: > On 2016/7/21 9:52, Haojian Zhuang wrote: >> >> >> >> 在 07/21/2016 09:51 AM, Haojian Zhuang 写道: >>> >>> Hi Feng, >>> >>> I think the main difference is who to handle the CRC bits. In the >>> designware emmc/sd controller, the whole 128-bit value is loaded into >>> the four response registers. There's no any shift on the 128-bit value >>> to remove CRC. (Refer to: drivers/mmc/host/dw_mmc.c). >> >> >> I mean the implementation in linux. $Linux/drivers/mmc/host/dw_mmc.c >> >>> >>> In the eMMC spec, it only mentions R2 response in table. >>> >>> Bit position [127:1] >>> Width (bits) 127 >>> Value x >>> Description CID or CSD register incl. >>> internal CRC7 >>> It also doesn't mention that we need to shift response value for CSD >>> register. >>> >>> So I did this fixing patch. I think that shifting isn't common to >>> support all eMMC/SD controller IP. Without this patch, the eMMC stack >>> will only get shifted CSD register value. >>> It results in parse error. > > > As I checked the SDHC driver in linux, there's the same logic as you > implemented in EmmcDxe. > > Now the question is whether EmmcDxe is designed for common code of all > vendor's IP. If so, we need to provide a GetCsd() callback to handle > different implementations for different vendor. Do you mind that I append > the GetCsd() callback in EFI_SD_MMC_PASS_THRU_PROTOCOL to fix this issue? > Unfortunately, you cannot simply add methods to protocols that are defined by the UEFI spec. If the passthru protocol is lacking in functionality, we should work with the UEFI forum to get it amended.
On 2016/7/21 19:24, Ard Biesheuvel wrote: > On 21 July 2016 at 13:17, Haojian Zhuang <haojian.zhuang@linaro.org> wrote: >> On 2016/7/21 9:52, Haojian Zhuang wrote: >>> >>> >>> 在 07/21/2016 09:51 AM, Haojian Zhuang 写道: >>>> Hi Feng, >>>> >>>> I think the main difference is who to handle the CRC bits. In the >>>> designware emmc/sd controller, the whole 128-bit value is loaded into >>>> the four response registers. There's no any shift on the 128-bit value >>>> to remove CRC. (Refer to: drivers/mmc/host/dw_mmc.c). >>> >>> I mean the implementation in linux. $Linux/drivers/mmc/host/dw_mmc.c >>> >>>> In the eMMC spec, it only mentions R2 response in table. >>>> >>>> Bit position [127:1] >>>> Width (bits) 127 >>>> Value x >>>> Description CID or CSD register incl. >>>> internal CRC7 >>>> It also doesn't mention that we need to shift response value for CSD >>>> register. >>>> >>>> So I did this fixing patch. I think that shifting isn't common to >>>> support all eMMC/SD controller IP. Without this patch, the eMMC stack >>>> will only get shifted CSD register value. >>>> It results in parse error. >> >> As I checked the SDHC driver in linux, there's the same logic as you >> implemented in EmmcDxe. >> >> Now the question is whether EmmcDxe is designed for common code of all >> vendor's IP. If so, we need to provide a GetCsd() callback to handle >> different implementations for different vendor. Do you mind that I append >> the GetCsd() callback in EFI_SD_MMC_PASS_THRU_PROTOCOL to fix this issue? >> > Unfortunately, you cannot simply add methods to protocols that are > defined by the UEFI spec. If the passthru protocol is lacking in > functionality, we should work with the UEFI forum to get it amended. OK. Maybe we can do the same thing by another way. Now only SDHC needs to shift data for CSD register. We could parse EMMC_CID by EmmcGetCid() in EmmcGetCsd() function. What's your opinion? Best Regards Haojian
Hi Feng, I have to say that lots of SD controllers are not compatible to SDHC, too. Just look at $Linux/drivers/mmc/host. And too many vendors are using Designware eMMC/SD controller IP, like Samsung, ST, Hisilicon, ZTE, Rockchip, Altera, and so on. If the eMMC/SD stack only supports SDHC, it'll only benefit a few vendors. And it also means that vendors need to create different eMMC/SD stack to do the same thing. Best Regards Haojian 在 07/22/2016 08:56 AM, Tian, Feng 写道: > Hi, Haojian > > JEDEC org doesn't have a eMMC host controller spec. most of eMMC h/c vendors just reuse the SD host controller spec defined by SD Association. Of course there are also some variants on eMMC host controller IP which doesn't follow SD host controller spec perfectly. > > The intention of EDKII SD/MMC stack is to cover those HCs/Devices following standard SD/MMC specs. For your Designware case, You would have to have an override version as it doesn't follow SD/MMC specs. > > Thanks > Feng > > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Haojian Zhuang > Sent: Thursday, July 21, 2016 9:40 PM > To: Ard Biesheuvel <ard.biesheuvel@linaro.org>; Charles Garcia-Tobin <Charles.Garcia-Tobin@arm.com> > Cc: edk2-devel-01 <edk2-devel@lists.01.org> > Subject: Re: [edk2] [PATCH] EmmcBlockIo: fix to get CSD data > > On 2016/7/21 19:24, Ard Biesheuvel wrote: >> On 21 July 2016 at 13:17, Haojian Zhuang <haojian.zhuang@linaro.org> wrote: >>> On 2016/7/21 9:52, Haojian Zhuang wrote: >>>> >>>> >>>> 在 07/21/2016 09:51 AM, Haojian Zhuang 写道: >>>>> Hi Feng, >>>>> >>>>> I think the main difference is who to handle the CRC bits. In the >>>>> designware emmc/sd controller, the whole 128-bit value is loaded >>>>> into the four response registers. There's no any shift on the >>>>> 128-bit value to remove CRC. (Refer to: drivers/mmc/host/dw_mmc.c). >>>> >>>> I mean the implementation in linux. $Linux/drivers/mmc/host/dw_mmc.c >>>> >>>>> In the eMMC spec, it only mentions R2 response in table. >>>>> >>>>> Bit position [127:1] >>>>> Width (bits) 127 >>>>> Value x >>>>> Description CID or CSD register incl. >>>>> internal CRC7 It also doesn't mention >>>>> that we need to shift response value for CSD register. >>>>> >>>>> So I did this fixing patch. I think that shifting isn't common to >>>>> support all eMMC/SD controller IP. Without this patch, the eMMC >>>>> stack will only get shifted CSD register value. >>>>> It results in parse error. >>> >>> As I checked the SDHC driver in linux, there's the same logic as you >>> implemented in EmmcDxe. >>> >>> Now the question is whether EmmcDxe is designed for common code of >>> all vendor's IP. If so, we need to provide a GetCsd() callback to >>> handle different implementations for different vendor. Do you mind >>> that I append the GetCsd() callback in EFI_SD_MMC_PASS_THRU_PROTOCOL to fix this issue? >>> >> Unfortunately, you cannot simply add methods to protocols that are >> defined by the UEFI spec. If the passthru protocol is lacking in >> functionality, we should work with the UEFI forum to get it amended. > > OK. Maybe we can do the same thing by another way. Now only SDHC needs to > > shift data for CSD register. We could parse EMMC_CID by EmmcGetCid() in > EmmcGetCsd() > > function. What's your opinion? > > > Best Regards > > Haojian > > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel >
diff --git a/MdeModulePkg/Bus/Sd/EmmcDxe/EmmcBlockIo.c b/MdeModulePkg/Bus/Sd/EmmcDxe/EmmcBlockIo.c index fc705e1..fe85627 100644 --- a/MdeModulePkg/Bus/Sd/EmmcDxe/EmmcBlockIo.c +++ b/MdeModulePkg/Bus/Sd/EmmcDxe/EmmcBlockIo.c @@ -191,9 +191,9 @@ EmmcGetCsd ( Status = PassThru->PassThru (PassThru, Device->Slot, &Packet, NULL); if (!EFI_ERROR (Status)) { // - // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12. + // Copy 128bit data for CSD structure. // - CopyMem (((UINT8*)Csd) + 1, &SdMmcStatusBlk.Resp0, sizeof (EMMC_CSD) - 1); + CopyMem ((VOID*)Csd, &SdMmcStatusBlk.Resp0, sizeof (EMMC_CSD)); } return Status;
The CSD structure is a 128-bit structure. But EmmcGetCsd() only loads 120 bits with 8-bit offset. Now fix it. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> --- MdeModulePkg/Bus/Sd/EmmcDxe/EmmcBlockIo.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel