@@ -1,4 +1,5 @@
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
/ {
#address-cells = <1>;
@@ -57,18 +58,18 @@ gpio2: gpio@14 {
no-output;
};
- nand@0 {
+ nand-controller@0 {
compatible = "gpio-control-nand";
nand-on-flash-bbt;
nand-ecc-mode = "soft_bch";
nand-ecc-step-size = <512>;
nand-ecc-strength = <4>;
reg = <0x0 4>;
- gpios = <&gpio2 0 0>, /* rdy */
- <&gpio1 1 0>, /* nce */
- <&gpio1 2 0>, /* ale */
- <&gpio1 3 0>, /* cle */
- <&gpio1 4 0>; /* nwp */
+ rdy-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
+ ce-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+ ale-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ cle-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
};
serial@80000 {
This changes the GPIOs defined in the device tree to recommended practice, which is also what the Linux NAND GPIO driver is actually using. In the process, fix up the CE and WP lines to be active low, as is required for proper hardware description. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> --- arch/mips/boot/dts/ni/169445.dts | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-)