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[1/1] target/arm: enable FEAT_RNG on Neoverse-N2

Message ID 20231114103443.1652308-1-marcin.juszkiewicz@linaro.org
State New
Headers show
Series [1/1] target/arm: enable FEAT_RNG on Neoverse-N2 | expand

Commit Message

Marcin Juszkiewicz Nov. 14, 2023, 10:34 a.m. UTC
I noticed that Neoverse-V1 has FEAT_RNG enabled so let enable it also on
Neoverse-N2.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
 target/arm/tcg/cpu64.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Richard Henderson Nov. 14, 2023, 6:23 p.m. UTC | #1
On 11/14/23 02:34, Marcin Juszkiewicz wrote:
> I noticed that Neoverse-V1 has FEAT_RNG enabled so let enable it also on
> Neoverse-N2.
> 
> Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
> ---
>   target/arm/tcg/cpu64.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
> index 08db1dbcc7..fcda99e158 100644
> --- a/target/arm/tcg/cpu64.c
> +++ b/target/arm/tcg/cpu64.c
> @@ -1018,7 +1018,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
>       cpu->isar.id_aa64dfr1  = 0;
>       cpu->id_aa64afr0       = 0;
>       cpu->id_aa64afr1       = 0;
> -    cpu->isar.id_aa64isar0 = 0x0221111110212120ull; /* with Crypto */
> +    cpu->isar.id_aa64isar0 = 0x1221111110212120ull; /* with Crypto and FEAT_RNG */
>       cpu->isar.id_aa64isar1 = 0x0011111101211052ull;
>       cpu->isar.id_aa64mmfr0 = 0x0000022200101125ull;
>       cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~
Peter Maydell Nov. 20, 2023, 3:09 p.m. UTC | #2
On Tue, 14 Nov 2023 at 10:34, Marcin Juszkiewicz
<marcin.juszkiewicz@linaro.org> wrote:
>
> I noticed that Neoverse-V1 has FEAT_RNG enabled so let enable it also on
> Neoverse-N2.
>
> Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
> ---
>  target/arm/tcg/cpu64.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
> index 08db1dbcc7..fcda99e158 100644
> --- a/target/arm/tcg/cpu64.c
> +++ b/target/arm/tcg/cpu64.c
> @@ -1018,7 +1018,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
>      cpu->isar.id_aa64dfr1  = 0;
>      cpu->id_aa64afr0       = 0;
>      cpu->id_aa64afr1       = 0;
> -    cpu->isar.id_aa64isar0 = 0x0221111110212120ull; /* with Crypto */
> +    cpu->isar.id_aa64isar0 = 0x1221111110212120ull; /* with Crypto and FEAT_RNG */
>      cpu->isar.id_aa64isar1 = 0x0011111101211052ull;
>      cpu->isar.id_aa64mmfr0 = 0x0000022200101125ull;
>      cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
> --
> 2.41.0



Applied to target-arm.next, thanks.

-- PMM
diff mbox series

Patch

diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 08db1dbcc7..fcda99e158 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -1018,7 +1018,7 @@  static void aarch64_neoverse_n2_initfn(Object *obj)
     cpu->isar.id_aa64dfr1  = 0;
     cpu->id_aa64afr0       = 0;
     cpu->id_aa64afr1       = 0;
-    cpu->isar.id_aa64isar0 = 0x0221111110212120ull; /* with Crypto */
+    cpu->isar.id_aa64isar0 = 0x1221111110212120ull; /* with Crypto and FEAT_RNG */
     cpu->isar.id_aa64isar1 = 0x0011111101211052ull;
     cpu->isar.id_aa64mmfr0 = 0x0000022200101125ull;
     cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;