@@ -232,8 +232,8 @@ mt76_dma_add_rx_buf(struct mt76_dev *dev, struct mt76_queue *q,
struct mt76_queue_entry *entry = &q->entry[q->head];
struct mt76_txwi_cache *txwi = NULL;
struct mt76_desc *desc;
- u32 buf1 = 0, ctrl;
int idx = q->head;
+ u32 buf1, ctrl;
int rx_token;
if (mt76_queue_is_wed_rro_ind(q)) {
@@ -246,6 +246,7 @@ mt76_dma_add_rx_buf(struct mt76_dev *dev, struct mt76_queue *q,
desc = &q->desc[q->head];
ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
+ buf1 = FIELD_PREP(MT_DMA_CTL_SDP0_H, buf->addr >> 32);
if (mt76_queue_is_wed_rx(q)) {
txwi = mt76_get_rxwi(dev);
@@ -312,11 +313,14 @@ mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
entry->dma_len[0] = buf[0].len;
ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
+ info |= FIELD_PREP(MT_DMA_CTL_SDP0_H, buf[0].addr >> 32);
if (i < nbufs - 1) {
entry->dma_addr[1] = buf[1].addr;
entry->dma_len[1] = buf[1].len;
buf1 = buf[1].addr;
ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
+ info |= FIELD_PREP(MT_DMA_CTL_SDP1_H,
+ buf[1].addr >> 32);
if (buf[1].skip_unmap)
entry->skip_buf1 = true;
}
@@ -19,6 +19,8 @@
#define MT_DMA_CTL_TO_HOST_A BIT(12)
#define MT_DMA_CTL_DROP BIT(14)
#define MT_DMA_CTL_TOKEN GENMASK(31, 16)
+#define MT_DMA_CTL_SDP1_H GENMASK(19, 16)
+#define MT_DMA_CTL_SDP0_H GENMASK(3, 0)
#define MT_DMA_CTL_WO_DROP BIT(8)
#define MT_DMA_PPE_CPU_REASON GENMASK(15, 11)
@@ -142,8 +142,9 @@ u32 mt76_mmio_wed_init_rx_buf(struct mtk_wed_device *wed, int size)
goto unmap;
}
- desc->token |= cpu_to_le32(FIELD_PREP(MT_DMA_CTL_TOKEN,
- token));
+ token = FIELD_PREP(MT_DMA_CTL_TOKEN, token) |
+ FIELD_PREP(MT_DMA_CTL_SDP0_H, addr >> 32);
+ desc->token |= cpu_to_le32(token);
desc++;
}
@@ -183,7 +183,7 @@ struct mt76_queue_entry {
struct urb *urb;
int buf_sz;
};
- u32 dma_addr[2];
+ dma_addr_t dma_addr[2];
u16 dma_len[2];
u16 wcid;
bool skip_buf0:1;
@@ -259,6 +259,9 @@ enum tx_mgnt_type {
#define MT_TXD9_WLAN_IDX GENMASK(23, 8)
+#define MT_TXP_BUF_LEN GENMASK(11, 0)
+#define MT_TXP_DMA_ADDR_H GENMASK(15, 12)
+
#define MT_TX_RATE_STBC BIT(14)
#define MT_TX_RATE_NSS GENMASK(13, 10)
#define MT_TX_RATE_MODE GENMASK(9, 6)
@@ -203,7 +203,8 @@ void mt7996_dma_start(struct mt7996_dev *dev, bool reset, bool wed_reset)
if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed))
mt76_set(dev, MT_WFDMA0_GLO_CFG,
MT_WFDMA0_GLO_CFG_TX_DMA_EN |
- MT_WFDMA0_GLO_CFG_OMIT_TX_INFO);
+ MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
+ MT_WFDMA0_GLO_CFG_EXT_EN);
else
mt76_set(dev, MT_WFDMA0_GLO_CFG,
MT_WFDMA0_GLO_CFG_TX_DMA_EN |
@@ -216,7 +217,8 @@ void mt7996_dma_start(struct mt7996_dev *dev, bool reset, bool wed_reset)
MT_WFDMA0_GLO_CFG_TX_DMA_EN |
MT_WFDMA0_GLO_CFG_RX_DMA_EN |
MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
- MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
+ MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 |
+ MT_WFDMA0_GLO_CFG_EXT_EN);
}
/* enable interrupts for TX/RX rings */
@@ -994,8 +994,12 @@ int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
txp = (struct mt76_connac_txp_common *)(txwi + MT_TXD_SIZE);
for (i = 0; i < nbuf; i++) {
+ u16 len = FIELD_PREP(MT_TXP_BUF_LEN, tx_info->buf[i + 1].len) |
+ FIELD_PREP(MT_TXP_DMA_ADDR_H,
+ tx_info->buf[i + 1].addr >> 32);
+
txp->fw.buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr);
- txp->fw.len[i] = cpu_to_le16(tx_info->buf[i + 1].len);
+ txp->fw.len[i] = cpu_to_le16(len);
}
txp->fw.nbuf = nbuf;
@@ -235,7 +235,6 @@ int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr,
struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
struct pci_dev *pci_dev = pdev_ptr;
u32 hif1_ofs = 0;
- int ret;
if (!wed_enable)
return 0;
@@ -355,14 +354,6 @@ int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr,
*irq = wed->irq;
dev->mt76.dma_dev = wed->dev;
- ret = dma_set_mask(wed->dev, DMA_BIT_MASK(32));
- if (ret)
- return ret;
-
- ret = dma_set_coherent_mask(wed->dev, DMA_BIT_MASK(32));
- if (ret)
- return ret;
-
return 1;
#else
return 0;
@@ -107,7 +107,11 @@ static int mt7996_pci_probe(struct pci_dev *pdev,
pci_set_master(pdev);
- ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
+ ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36));
+ if (ret)
+ return ret;
+
+ ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
if (ret)
return ret;
@@ -375,9 +375,10 @@ enum base_rev {
#define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208)
#define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
#define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2)
-#define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28)
-#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27)
#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21)
+#define MT_WFDMA0_GLO_CFG_EXT_EN BIT(26)
+#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27)
+#define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28)
#define WF_WFDMA0_GLO_CFG_EXT0 MT_WFDMA0(0x2b0)
#define WF_WFDMA0_GLO_CFG_EXT0_RX_WB_RXD BIT(18)